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authorarved <arved@FreeBSD.org>2004-11-05 21:16:52 +0800
committerarved <arved@FreeBSD.org>2004-11-05 21:16:52 +0800
commitc55dccbbd55f7623678e08f8503f8968ffadcac4 (patch)
treec41a772e0c45cd437f7f9734d99cbe5139473d60 /cad/iverilog/Makefile
parent7b74549775af3ac15cbd8532935b6fecb118180f (diff)
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Update to 0.8
PR: 72949 Submitted by: Joachim Strombergson <watchman@ludd.ltu.se>
Diffstat (limited to 'cad/iverilog/Makefile')
-rw-r--r--cad/iverilog/Makefile6
1 files changed, 3 insertions, 3 deletions
diff --git a/cad/iverilog/Makefile b/cad/iverilog/Makefile
index c7e3001dc9ad..40d7f16f6b1d 100644
--- a/cad/iverilog/Makefile
+++ b/cad/iverilog/Makefile
@@ -7,10 +7,10 @@
#
PORTNAME= iverilog
-PORTVERSION= 0.7.20040606
+PORTVERSION= 0.8
CATEGORIES= cad
-MASTER_SITES= ftp://icarus.com/pub/eda/verilog/snapshots/
-DISTNAME= verilog-20040606
+MASTER_SITES= ftp://icarus.com/pub/eda/verilog/v$(PORTVERSION)/
+DISTNAME= verilog-$(PORTVERSION)
MAINTAINER= watchman@ludd.luth.se
COMMENT= A Verilog simulation and synthesis tool