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| author | olgeni <olgeni@FreeBSD.org> | 2010-07-30 22:51:37 +0800 |
|---|---|---|
| committer | olgeni <olgeni@FreeBSD.org> | 2010-07-30 22:51:37 +0800 |
| commit | 621db45e4d90c2bf3ecc5724dce25a83c0ad42de (patch) | |
| tree | 0bd4a8808b9fe3fc9192198a8f796fbd6de8f24e /cad/iverilog | |
| parent | 4c4577e3b8491986e30bade0e4c6253543386f76 (diff) | |
| download | freebsd-ports-gnome-621db45e4d90c2bf3ecc5724dce25a83c0ad42de.tar.gz freebsd-ports-gnome-621db45e4d90c2bf3ecc5724dce25a83c0ad42de.tar.zst freebsd-ports-gnome-621db45e4d90c2bf3ecc5724dce25a83c0ad42de.zip | |
Fix a few typos in ports/cad.
Diffstat (limited to 'cad/iverilog')
| -rw-r--r-- | cad/iverilog/pkg-descr | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/cad/iverilog/pkg-descr b/cad/iverilog/pkg-descr index 39739afe9bc5..cdc2c152ac1e 100644 --- a/cad/iverilog/pkg-descr +++ b/cad/iverilog/pkg-descr @@ -1,5 +1,5 @@ Icarus Verilog is a Verilog simulation and synthesis tool. It -operates as a compiler, compiling source code writen in Verilog +operates as a compiler, compiling source code written in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate C++ code that is compiled and linked with a run time library (called "vvm") then executed as a command to |