cad/p5-Verilog-Perl: 3.404 -> 3.418

Changes:
  http://cpansearch.perl.org/src/WSNYDER/Verilog-Perl-3.418/Changes
  Removed dependency of gcc. Now, p5-Verilog-Perl compiles with clang.

PR:		207050
Submitted by:	otacilio.neto@ee.ufcg.edu.br (maintainer)

6 files changed, 40 insertions, 43 deletions

diff --git a/cad/p5-Verilog-Perl/Makefile b/cad/p5-Verilog-Perl/Makefile
index 2d7115e4b5d5..247981d4d8be 100644
--- a/cad/p5-Verilog-Perl/Makefile
+++ b/cad/p5-Verilog-Perl/Makefile
@@ -1,9 +1,8 @@
-# Created by: Otacilio de Araujo Ramos Neto <otacilio.neto@ee.ufcg.edu.br>
+# Created by: Otacilio de Araujo Ramos Neto <otacilio.neto@bsd.com.br>
 # $FreeBSD$
 
 PORTNAME=	Verilog-Perl
-PORTVERSION=	3.404
-PORTREVISION=	1
+PORTVERSION=	3.418
 CATEGORIES=	cad perl5
 MASTER_SITES=	CPAN
 PKGNAMEPREFIX=	p5-
@@ -15,7 +14,6 @@ BUILD_DEPENDS=	flex>=2.5.35:${PORTSDIR}/textproc/flex
 
 USES=		bison gmake perl5
 USE_PERL5=	configure
-USE_GCC=	any
 CONFIGURE_ENV=	CXX=${CXX}\
 		CPP=${CPP}\
 		CC=${CC}
diff --git a/cad/p5-Verilog-Perl/distinfo b/cad/p5-Verilog-Perl/distinfo
index 3b42dfc2b6f2..eb4d6f49483e 100644
--- a/cad/p5-Verilog-Perl/distinfo
+++ b/cad/p5-Verilog-Perl/distinfo
@@ -1,2 +1,2 @@
-SHA256 (Verilog-Perl-3.404.tar.gz) = 4eddc21a965019eecc2200e251186f9d8bd0643485d12feda7d0b26a328650d0
-SIZE (Verilog-Perl-3.404.tar.gz) = 558496
+SHA256 (Verilog-Perl-3.418.tar.gz) = 19eb60cb211fe6dbe6f9705f973e72c9ffd370399c39f0871652d4bee61492e8
+SIZE (Verilog-Perl-3.418.tar.gz) = 562256
diff --git a/cad/p5-Verilog-Perl/files/patch-Makefile.PL b/cad/p5-Verilog-Perl/files/patch-Makefile.PL
index a9ff01e0296f..d2a20a46cb96 100644
--- a/cad/p5-Verilog-Perl/files/patch-Makefile.PL
+++ b/cad/p5-Verilog-Perl/files/patch-Makefile.PL
@@ -1,6 +1,6 @@
---- Makefile.PL	2014-03-11 19:59:40.000000000 -0300
-+++ Makefile.PL	2014-06-25 11:18:59.000000000 -0300
-@@ -11,7 +11,7 @@
+--- Makefile.PL.orig	2016-02-02 23:36:13 UTC
++++ Makefile.PL
+@@ -11,7 +11,7 @@ use Config;
  
  sub MY::postamble {
      my $out="";
@@ -8,8 +8,8 @@
 +    # Note OPTIMIZE is passed from upper gmakefile, so this code needed there too.
      # -O2 optimization seems unreasonably slow on nearly every platform.  I give up.
      my $optimize = $Config{optimize};  $optimize =~ s/(^| )-O2( |$)/\1-O\2/g;
-     $out .= "OPTIMIZE = $optimize\n";
-@@ -82,6 +82,8 @@
+     # pass hardening flags
+@@ -86,6 +86,8 @@ cppcheck: $(CPPCHECK_DEP)
      return $out;
  }
  
@@ -18,7 +18,7 @@
  my $fail;
  local $! = undef;
  my $have_gen = -d "Preproc/gen";
-@@ -93,7 +95,7 @@
+@@ -97,7 +99,7 @@ my $have_gen = -d "Preproc/gen";
      if ($have_gen) { warn "\n-Note: 'bison' must be installed to build from sources\n"; }
      else { $fail=1; warn "\n%Error: 'bison' must be installed to build\n\n"; }
  }
@@ -27,7 +27,7 @@
  if ($fail) {
      if ($ENV{AUTOMATED_TESTING}) {
  	exit(0);
-@@ -135,8 +137,8 @@
+@@ -139,7 +141,7 @@ WriteMakefile(
  			},
  	      );
  
@@ -36,4 +36,3 @@
  if ($? || $mkv !~ /GNU Make/i) {
      warn "-Important: Now type 'gmake MAKE=gmake' as this package requires GNU Make\n";
  }
- 1;
diff --git a/cad/p5-Verilog-Perl/files/patch-Parser__Makefile.PL b/cad/p5-Verilog-Perl/files/patch-Parser__Makefile.PL
index 550fc0d9dc1f..1b5f1fd9ca16 100644
--- a/cad/p5-Verilog-Perl/files/patch-Parser__Makefile.PL
+++ b/cad/p5-Verilog-Perl/files/patch-Parser__Makefile.PL
@@ -1,6 +1,6 @@
---- Parser/Makefile.PL	2014-03-11 19:59:40.000000000 -0300
-+++ Parser/Makefile.PL	2014-06-25 11:19:19.000000000 -0300
-@@ -9,13 +9,15 @@
+--- Parser/Makefile.PL.orig	2016-02-02 23:36:13 UTC
++++ Parser/Makefile.PL
+@@ -9,13 +9,15 @@ use Config;
  
  sub MY::postamble {
      my $out;
@@ -17,7 +17,7 @@
      }
      # Note OPTIMIZE is passed from upper makefile, so this code needed there too.
      my $optimize = $Config{optimize};  $optimize =~ s/(^| )-O2( |$)/\1-O\2/g;
-@@ -46,7 +48,7 @@
+@@ -50,7 +52,7 @@ sub MY::postamble {
      $out .= "${cmt}CFLAGS += -DFLEX_DEBUG\n";
      $out .= "LEXFLAGS += -d\n";
      $out .= '
diff --git a/cad/p5-Verilog-Perl/files/patch-Preproc__Makefile.PL b/cad/p5-Verilog-Perl/files/patch-Preproc__Makefile.PL
index 747ba533da79..083af1c04638 100644
--- a/cad/p5-Verilog-Perl/files/patch-Preproc__Makefile.PL
+++ b/cad/p5-Verilog-Perl/files/patch-Preproc__Makefile.PL
@@ -1,6 +1,6 @@
---- Preproc/Makefile.PL	2014-03-11 19:59:40.000000000 -0300
-+++ Preproc/Makefile.PL	2014-06-25 11:19:37.000000000 -0300
-@@ -9,13 +9,14 @@
+--- Preproc/Makefile.PL.orig	2016-02-02 23:36:13 UTC
++++ Preproc/Makefile.PL
+@@ -9,13 +9,14 @@ use Config;
  
  sub MY::postamble {
      my $out;
@@ -16,7 +16,7 @@
      }
      # Note OPTIMIZE is passed from upper makefile, so this code needed there too.
      my $optimize = $Config{optimize};  $optimize =~ s/(^| )-O2( |$)/\1-O\2/g;
-@@ -46,7 +47,7 @@
+@@ -50,7 +51,7 @@ sub MY::postamble {
      $out .= "${cmt}CFLAGS += -DFLEX_DEBUG\n";
      $out .= "${cmt}LEXFLAGS += -d\n";
      $out .= '
diff --git a/cad/p5-Verilog-Perl/pkg-plist b/cad/p5-Verilog-Perl/pkg-plist
index 77e84f107b6a..c0315353a1b0 100644
--- a/cad/p5-Verilog-Perl/pkg-plist
+++ b/cad/p5-Verilog-Perl/pkg-plist
@@ -3,27 +3,6 @@ bin/vpassert
 bin/vppreproc
 bin/vrename
 bin/vsplitmodule
-%%PERL5_MAN3%%/Verilog::EditFiles.3.gz
-%%PERL5_MAN3%%/Verilog::Getopt.3.gz
-%%PERL5_MAN3%%/Verilog::Language.3.gz
-%%PERL5_MAN3%%/Verilog::Netlist.3.gz
-%%PERL5_MAN3%%/Verilog::Netlist::Cell.3.gz
-%%PERL5_MAN3%%/Verilog::Netlist::ContAssign.3.gz
-%%PERL5_MAN3%%/Verilog::Netlist::Defparam.3.gz
-%%PERL5_MAN3%%/Verilog::Netlist::File.3.gz
-%%PERL5_MAN3%%/Verilog::Netlist::Interface.3.gz
-%%PERL5_MAN3%%/Verilog::Netlist::Logger.3.gz
-%%PERL5_MAN3%%/Verilog::Netlist::ModPort.3.gz
-%%PERL5_MAN3%%/Verilog::Netlist::Module.3.gz
-%%PERL5_MAN3%%/Verilog::Netlist::Net.3.gz
-%%PERL5_MAN3%%/Verilog::Netlist::Pin.3.gz
-%%PERL5_MAN3%%/Verilog::Netlist::Port.3.gz
-%%PERL5_MAN3%%/Verilog::Netlist::Subclass.3.gz
-%%PERL5_MAN3%%/Verilog::Parser.3.gz
-%%PERL5_MAN3%%/Verilog::Preproc.3.gz
-%%PERL5_MAN3%%/Verilog::SigParser.3.gz
-%%PERL5_MAN3%%/Verilog::Std.3.gz
-%%PERL5_MAN3%%/Verilog::Verilog-Perl.3.gz
 %%SITE_ARCH%%/Verilog/EditFiles.pm
 %%SITE_ARCH%%/Verilog/Getopt.pm
 %%SITE_ARCH%%/Verilog/Language.pm
@@ -51,3 +30,24 @@ bin/vsplitmodule
 %%PERL5_MAN1%%/vpassert.1.gz
 %%PERL5_MAN1%%/vppreproc.1.gz
 %%PERL5_MAN1%%/vrename.1.gz
+%%PERL5_MAN3%%/Verilog::EditFiles.3.gz
+%%PERL5_MAN3%%/Verilog::Getopt.3.gz
+%%PERL5_MAN3%%/Verilog::Language.3.gz
+%%PERL5_MAN3%%/Verilog::Netlist.3.gz
+%%PERL5_MAN3%%/Verilog::Netlist::Cell.3.gz
+%%PERL5_MAN3%%/Verilog::Netlist::ContAssign.3.gz
+%%PERL5_MAN3%%/Verilog::Netlist::Defparam.3.gz
+%%PERL5_MAN3%%/Verilog::Netlist::File.3.gz
+%%PERL5_MAN3%%/Verilog::Netlist::Interface.3.gz
+%%PERL5_MAN3%%/Verilog::Netlist::Logger.3.gz
+%%PERL5_MAN3%%/Verilog::Netlist::ModPort.3.gz
+%%PERL5_MAN3%%/Verilog::Netlist::Module.3.gz
+%%PERL5_MAN3%%/Verilog::Netlist::Net.3.gz
+%%PERL5_MAN3%%/Verilog::Netlist::Pin.3.gz
+%%PERL5_MAN3%%/Verilog::Netlist::Port.3.gz
+%%PERL5_MAN3%%/Verilog::Netlist::Subclass.3.gz
+%%PERL5_MAN3%%/Verilog::Parser.3.gz
+%%PERL5_MAN3%%/Verilog::Preproc.3.gz
+%%PERL5_MAN3%%/Verilog::SigParser.3.gz
+%%PERL5_MAN3%%/Verilog::Std.3.gz
+%%PERL5_MAN3%%/Verilog::Verilog-Perl.3.gz