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authorpawel <pawel@FreeBSD.org>2016-07-28 01:04:44 +0800
committerpawel <pawel@FreeBSD.org>2016-07-28 01:04:44 +0800
commit00d4633212866d615560af67dddc3c95e74c82bb (patch)
tree2a90c11118040206558158b32ed20bc5a2c7fa24 /cad
parenteaaa7585ce243f82e963997533cedfc994dcc9d5 (diff)
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- Change maintainer email [1]
- Add LICENSE info [1] - Strip more binaries [1] - No need to include bsd.port.pre.mk PR: 210844 [1] Submitted by: otacilio.neto@bsd.com.br (maintainer)
Diffstat (limited to 'cad')
-rw-r--r--cad/p5-Verilog-Perl/Makefile9
1 files changed, 5 insertions, 4 deletions
diff --git a/cad/p5-Verilog-Perl/Makefile b/cad/p5-Verilog-Perl/Makefile
index 166782690a27..ef676c8a61e1 100644
--- a/cad/p5-Verilog-Perl/Makefile
+++ b/cad/p5-Verilog-Perl/Makefile
@@ -7,9 +7,11 @@ CATEGORIES= cad perl5
MASTER_SITES= CPAN
PKGNAMEPREFIX= p5-
-MAINTAINER= otacilio.neto@ee.ufcg.edu.br
+MAINTAINER= otacilio.neto@bsd.com.br
COMMENT= Building point for Verilog support in the Perl language
+LICENSE= LGPL3
+
BUILD_DEPENDS= flex>=2.5.35:textproc/flex
USES= bison gmake perl5
@@ -18,12 +20,11 @@ CONFIGURE_ENV= CXX=${CXX}\
CPP=${CPP}\
CC=${CC}
-.include <bsd.port.pre.mk>
-
post-install:
${STRIP_CMD} ${STAGEDIR}${PREFIX}/${SITE_ARCH_REL}/auto/Verilog/Parser/*.so
+ ${STRIP_CMD} ${STAGEDIR}${PREFIX}/${SITE_ARCH_REL}/auto/Verilog/Preproc/*.so
regression-test: build
make test -C ${WRKSRC}
-.include <bsd.port.post.mk>
+.include <bsd.port.mk>