The Verilog-Perl library is a building point for Verilog support in the Perl

language. It includes:
* Verilog::Getopt which parses command line options similar to C++ and VCS.
* Verilog::Language which knows the language keywords and parses numbers.
* Verilog::Netlist which builds netlists out of Verilog files. This allows
  easy scripts to determine things such as the hierarchy of modules.
* Verilog::Parser invokes callbacks for language tokens.
* Verilog::Preproc preprocesses the language, and allows reading
  post-processed files right from Perl without temporary files.
* vpassert inserts PLIish warnings and assertions for any simulator.
* vppreproc preprocesses the complete Verilog 2001 and SystemVerilog language.
* vrename renames and cross-references Verilog symbols. Vrename creates Verilog
  cross references and makes it easy to rename signal and module names across
  multiple files. Vrename uses a simple and efficient three step process.
  First, you run vrename to create a list of signals in the design. You then
  edit this list, changing as many symbols as you wish. Vrename is then run a
  second time to apply the changes.

WWW:	http://www.veripool.org/wiki/verilog-perl

PR:		ports/134124
Submitted by:	Otacílio de Araújo Ramos Neto <otacilio.neto at ee.ufcg.edu.br>

5 files changed, 98 insertions, 0 deletions

diff --git a/cad/Makefile b/cad/Makefile
index 767c85da2c1e..c2aefb8acc5a 100644
--- a/cad/Makefile
+++ b/cad/Makefile
@@ -63,6 +63,7 @@
     SUBDIR += opencascade-tutorial
     SUBDIR += oregano
     SUBDIR += p5-GDS2
+    SUBDIR += p5-Verilog-Perl
     SUBDIR += pcb
     SUBDIR += pdnmesh
     SUBDIR += pythoncad
diff --git a/cad/p5-Verilog-Perl/Makefile b/cad/p5-Verilog-Perl/Makefile
new file mode 100644
index 000000000000..16867f033ce2
--- /dev/null
+++ b/cad/p5-Verilog-Perl/Makefile
@@ -0,0 +1,42 @@
+# New ports collection makefile for:   Verilog-Perl
+# Date created:                11 Apr 2009
+# Whom:                        Otacílio de Araújo Ramos Neto <otacilio.neto@ee.ufcg.edu.br>
+#
+# $FreeBSD$
+#
+
+PORTNAME=	Verilog-Perl
+PORTVERSION=	3.210
+CATEGORIES=	cad perl5
+MASTER_SITES=	CPAN
+PKGNAMEPREFIX=	p5-
+
+MAINTAINER=	otacilio.neto@ee.ufcg.edu.br
+COMMENT=	Building point for Verilog support in the Perl language
+
+USE_GMAKE=	yes
+USE_PERL5=	yes
+
+PERL_CONFIGURE=	yes
+
+MAN1=	vhier.1 vpassert.1 vppreproc.1 vrename.1
+
+MAN3=	Verilog::EditFiles.3 Verilog::Netlist::Logger.3 \
+	Verilog::Parser.3 Verilog::Getopt.3 Verilog::Netlist::Module.3 \
+	Verilog::Preproc.3 Verilog::Language.3 Verilog::Netlist::Net.3 \
+	Verilog::SigParser.3 Verilog::Netlist.3 Verilog::Netlist::Pin.3 \
+	Verilog::Netlist::Cell.3 Verilog::Netlist::Port.3 \
+	Verilog::Netlist::File.3 Verilog::Netlist::Subclass.3 \
+	Verilog::Verilog-Perl.3 Verilog::Netlist::Interface.3 Verilog::Std.3
+
+post-patch:
+	@${REINPLACE_CMD} -e '/EXE_FILES/ s/ vsplitmodule//' \
+		${WRKSRC}/Makefile.PL
+
+post-build:
+	cd ${WRKSRC} && make test
+
+test:
+	make post-build
+
+.include <bsd.port.mk>
diff --git a/cad/p5-Verilog-Perl/distinfo b/cad/p5-Verilog-Perl/distinfo
new file mode 100644
index 000000000000..6bdd7f294e52
--- /dev/null
+++ b/cad/p5-Verilog-Perl/distinfo
@@ -0,0 +1,3 @@
+MD5 (Verilog-Perl-3.210.tar.gz) = 4facca9c30bfdd21d03024e4272ab9c8
+SHA256 (Verilog-Perl-3.210.tar.gz) = 814bedd604017824966d98e3a81c494994d1969f8217f0349ca58f234fed8ede
+SIZE (Verilog-Perl-3.210.tar.gz) = 205250
diff --git a/cad/p5-Verilog-Perl/pkg-descr b/cad/p5-Verilog-Perl/pkg-descr
new file mode 100644
index 000000000000..ea471de4d4fd
--- /dev/null
+++ b/cad/p5-Verilog-Perl/pkg-descr
@@ -0,0 +1,19 @@
+The Verilog-Perl library is a building point for Verilog support in the Perl 
+language. It includes:
+* Verilog::Getopt which parses command line options similar to C++ and VCS.
+* Verilog::Language which knows the language keywords and parses numbers.
+* Verilog::Netlist which builds netlists out of Verilog files. This allows 
+  easy scripts to determine things such as the hierarchy of modules.
+* Verilog::Parser invokes callbacks for language tokens.
+* Verilog::Preproc preprocesses the language, and allows reading 
+  post-processed files right from Perl without temporary files.
+* vpassert inserts PLIish warnings and assertions for any simulator.
+* vppreproc preprocesses the complete Verilog 2001 and SystemVerilog language.
+* vrename renames and cross-references Verilog symbols. Vrename creates Verilog
+  cross references and makes it easy to rename signal and module names across 
+  multiple files. Vrename uses a simple and efficient three step process. 
+  First, you run vrename to create a list of signals in the design. You then 
+  edit this list, changing as many symbols as you wish. Vrename is then run a 
+  second time to apply the changes.
+
+WWW:	http://www.veripool.org/wiki/verilog-perl
diff --git a/cad/p5-Verilog-Perl/pkg-plist b/cad/p5-Verilog-Perl/pkg-plist
new file mode 100644
index 000000000000..e0f459aca3d2
--- /dev/null
+++ b/cad/p5-Verilog-Perl/pkg-plist
@@ -0,0 +1,33 @@
+bin/vhier
+bin/vpassert
+bin/vppreproc
+bin/vrename
+%%SITE_PERL%%/mach/Verilog/EditFiles.pm
+%%SITE_PERL%%/mach/Verilog/Getopt.pm
+%%SITE_PERL%%/mach/Verilog/Language.pm
+%%SITE_PERL%%/mach/Verilog/Netlist.pm
+%%SITE_PERL%%/mach/Verilog/Netlist/Cell.pm
+%%SITE_PERL%%/mach/Verilog/Netlist/File.pm
+%%SITE_PERL%%/mach/Verilog/Netlist/Interface.pm
+%%SITE_PERL%%/mach/Verilog/Netlist/Logger.pm
+%%SITE_PERL%%/mach/Verilog/Netlist/Module.pm
+%%SITE_PERL%%/mach/Verilog/Netlist/Net.pm
+%%SITE_PERL%%/mach/Verilog/Netlist/Pin.pm
+%%SITE_PERL%%/mach/Verilog/Netlist/Port.pm
+%%SITE_PERL%%/mach/Verilog/Netlist/Subclass.pm
+%%SITE_PERL%%/mach/Verilog/Parser.pm
+%%SITE_PERL%%/mach/Verilog/Preproc.pm
+%%SITE_PERL%%/mach/Verilog/SigParser.pm
+%%SITE_PERL%%/mach/Verilog/Std.pm
+%%SITE_PERL%%/mach/Verilog/Verilog-Perl.pod
+%%SITE_PERL%%/mach/auto/Verilog/Language/.packlist
+%%SITE_PERL%%/mach/auto/Verilog/Parser/Parser.bs
+%%SITE_PERL%%/mach/auto/Verilog/Parser/Parser.so
+%%SITE_PERL%%/mach/auto/Verilog/Preproc/Preproc.bs
+%%SITE_PERL%%/mach/auto/Verilog/Preproc/Preproc.so
+@dirrm %%SITE_PERL%%/mach/auto/Verilog/Preproc
+@dirrm %%SITE_PERL%%/mach/auto/Verilog/Parser
+@dirrm %%SITE_PERL%%/mach/auto/Verilog/Language
+@dirrm %%SITE_PERL%%/mach/auto/Verilog
+@dirrm %%SITE_PERL%%/mach/Verilog/Netlist
+@dirrm %%SITE_PERL%%/mach/Verilog