Jspice3 is a circuit simulator developed to meet the needs of researchers

working with superconducting Josephson junction circuits, yet the program
has the flexibility and power to meet the needs of other technologies.

Jspice3 is an adaptation of the Berkeley Spice3f4 program, with added
features. One added feature is a built-in graphical input front end for
schematic capture. While displayed, simulations can be run and data
plotted through this graphical interface.

While not as powerful or as pretty as the Xic graphical interface, it
holds its own in functionality.

A significantly enhanced output plotting capability is provided, and
Jspice3 has enhanced script interpretation capability.

WWW:	http://www.wrcad.com/jspice3.html

PR:		ports/93958
Submitted by:	Pedro F. Giffuni

Pedro can't maintain this port anymore and Stanislav Sedov agree to maintiant it.

7 files changed, 150 insertions, 0 deletions

diff --git a/cad/Makefile b/cad/Makefile
index f82711ecf3ac..980c0877bf5a 100644
--- a/cad/Makefile
+++ b/cad/Makefile
@@ -38,6 +38,7 @@
     SUBDIR += impact
     SUBDIR += irsim
     SUBDIR += iverilog
+    SUBDIR += jspice3
     SUBDIR += kicad
     SUBDIR += leocad
     SUBDIR += libgeda
diff --git a/cad/jspice3/Makefile b/cad/jspice3/Makefile
new file mode 100644
index 000000000000..9bc9959439da
--- /dev/null
+++ b/cad/jspice3/Makefile
@@ -0,0 +1,39 @@
+# New ports collection makefile for:	Jspice
+# Date created:         26 Feb 2006
+# Whom:                 Pedro F. Giffuni
+#
+# $FreeBSD$
+#
+
+PORTNAME=	jspice3
+PORTVERSION=	2.5
+CATEGORIES=	cad
+MASTER_SITES=	http://www.wrcad.com/ftp/pub/	\
+		ftp://ftp.srware.com/pub/
+
+MAINTAINER=	ssedov@mbsd.msk.ru
+COMMENT=	An adaptation of the Berkeley Spice3f4 with superconductivity
+
+CONFLICTS=	spice-[0-9]*
+
+USE_XLIB=	yes
+
+pre-configure:
+	@${REINPLACE_CMD} -e 's+/usr/local+${PREFIX}+g ;	\
+	 s+-O -g+${CFLAGS}+g;' \
+		${WRKSRC}/conf/unixconf/mkheader.0
+
+do-build:
+	@(cd ${WRKSRC};${SETENV} ${MAKE_ENV} ${SH} build)
+
+do-install:
+	@(cd ${WRKSRC}/src/bin;${SETENV} ${MAKE_ENV} ${MAKE} install)
+
+post-install:
+.if !defined(NOPORTDOCS)
+	${MV} ${PREFIX}/lib/jspice3/examples ${EXAMPLESDIR}
+.else
+	${RM} -R ${PREFIX}/lib/jspice3/examples
+.endif
+
+.include <bsd.port.mk>
diff --git a/cad/jspice3/distinfo b/cad/jspice3/distinfo
new file mode 100644
index 000000000000..ed639df0da8f
--- /dev/null
+++ b/cad/jspice3/distinfo
@@ -0,0 +1,3 @@
+MD5 (jspice3-2.5.tar.gz) = 84b9a9ae8e438c73a4c1e3d8f502145a
+SHA256 (jspice3-2.5.tar.gz) = c32575f7686f6f9f252dce9b2385b79e69c3c253f913030a47ac4dce7f4bbdec
+SIZE (jspice3-2.5.tar.gz) = 1150509
diff --git a/cad/jspice3/files/patch-conf+unixconf+mkheader.0 b/cad/jspice3/files/patch-conf+unixconf+mkheader.0
new file mode 100644
index 000000000000..ba90de34b67e
--- /dev/null
+++ b/cad/jspice3/files/patch-conf+unixconf+mkheader.0
@@ -0,0 +1,11 @@
+--- conf/unixconf/mkheader.0.orig	Tue Feb 28 16:30:32 2006
++++ conf/unixconf/mkheader.0	Tue Feb 28 16:36:32 2006
+@@ -18,7 +18,7 @@
+ BUG_ADDR = stevew@srware.com
+ 
+ # name of host for remote spice runs
+-SPICE_HOST =
++SPICE_HOST = localhost
+ 
+ # spice daemon log file
+ SPICED_LOG = /tmp/spiced.log
diff --git a/cad/jspice3/files/patch-src+lib+fte+misccoms.c b/cad/jspice3/files/patch-src+lib+fte+misccoms.c
new file mode 100644
index 000000000000..713a397d2d3d
--- /dev/null
+++ b/cad/jspice3/files/patch-src+lib+fte+misccoms.c
@@ -0,0 +1,11 @@
+--- src/lib/fte/misccoms.c.orig	Tue Feb 28 16:57:47 2006
++++ src/lib/fte/misccoms.c	Tue Feb 28 16:59:28 2006
+@@ -284,7 +284,7 @@
+                                 pl->pl_title,
+                                 pl->pl_name);
+             }
+-            (void) SCEDfgets(buf,BSIZE_SP,cp_in,zz);
++            (void) SCEDfgets(buf, sizeof buf,cp_in,zz);
+ 
+             if ((*buf == 'y') || (*buf == 'Y') || (*buf == '\n'))
+                 byemesg();
diff --git a/cad/jspice3/pkg-descr b/cad/jspice3/pkg-descr
new file mode 100644
index 000000000000..a79ece1ceca5
--- /dev/null
+++ b/cad/jspice3/pkg-descr
@@ -0,0 +1,16 @@
+Jspice3 is a circuit simulator developed to meet the needs of researchers
+working with superconducting Josephson junction circuits, yet the program
+has the flexibility and power to meet the needs of other technologies.
+
+Jspice3 is an adaptation of the Berkeley Spice3f4 program, with added
+features. One added feature is a built-in graphical input front end for
+schematic capture. While displayed, simulations can be run and data
+plotted through this graphical interface.
+
+While not as powerful or as pretty as the Xic graphical interface, it 
+holds its own in functionality.
+
+A significantly enhanced output plotting capability is provided, and
+Jspice3 has enhanced script interpretation capability.
+
+WWW:	http://www.wrcad.com/jspice3.html
diff --git a/cad/jspice3/pkg-plist b/cad/jspice3/pkg-plist
new file mode 100644
index 000000000000..51c612eba7c5
--- /dev/null
+++ b/cad/jspice3/pkg-plist
@@ -0,0 +1,69 @@
+bin/jspice3
+bin/help
+bin/nutmeg
+bin/proc2mod
+bin/multidec
+bin/spiced
+bin/xeditor
+lib/jspice3/mfbcap
+lib/jspice3/news
+lib/jspice3/helpdir/spicehlp.txt
+lib/jspice3/sced/device.lib
+lib/jspice3/sced/model.lib
+lib/jspice3/sced/sced.rc
+lib/jspice3/scripts/margins
+lib/jspice3/scripts/merit
+lib/jspice3/scripts/optimize
+lib/jspice3/scripts/setplot
+lib/jspice3/scripts/spinit
+@dirrm lib/jspice3/helpdir
+@dirrm lib/jspice3/sced
+@dirrm lib/jspice3/scripts
+@dirrm lib/jspice3
+%%PORTDOCS%%%%EXAMPLESDIR%%/bjtnoise.cir
+%%PORTDOCS%%%%EXAMPLESDIR%%/bsim1tst.cir
+%%PORTDOCS%%%%EXAMPLESDIR%%/bsim2tst.cir
+%%PORTDOCS%%%%EXAMPLESDIR%%/diffpair.cir
+%%PORTDOCS%%%%EXAMPLESDIR%%/diodisto.cir
+%%PORTDOCS%%%%EXAMPLESDIR%%/ltra_1.cir
+%%PORTDOCS%%%%EXAMPLESDIR%%/ltra_2.cir
+%%PORTDOCS%%%%EXAMPLESDIR%%/ltra_3.cir
+%%PORTDOCS%%%%EXAMPLESDIR%%/mixdisto.cir
+%%PORTDOCS%%%%EXAMPLESDIR%%/mos6inv.cir
+%%PORTDOCS%%%%EXAMPLESDIR%%/mosamp2.cir
+%%PORTDOCS%%%%EXAMPLESDIR%%/mosmem.cir
+%%PORTDOCS%%%%EXAMPLESDIR%%/process.mod
+%%PORTDOCS%%%%EXAMPLESDIR%%/process.pro
+%%PORTDOCS%%%%EXAMPLESDIR%%/pz2.cir
+%%PORTDOCS%%%%EXAMPLESDIR%%/pzt.cir
+%%PORTDOCS%%%%EXAMPLESDIR%%/rc.cir
+%%PORTDOCS%%%%EXAMPLESDIR%%/rca3040.cir
+%%PORTDOCS%%%%EXAMPLESDIR%%/resnoise.cir
+%%PORTDOCS%%%%EXAMPLESDIR%%/rtlinv.cir
+%%PORTDOCS%%%%EXAMPLESDIR%%/schmitt.cir
+%%PORTDOCS%%%%EXAMPLESDIR%%/simplepz.cir
+%%PORTDOCS%%%%EXAMPLESDIR%%/testc.cir
+%%PORTDOCS%%%%EXAMPLESDIR%%/cryocmos/cryo_model.lib
+%%PORTDOCS%%%%EXAMPLESDIR%%/cryocmos/nmos_test.sp
+%%PORTDOCS%%%%EXAMPLESDIR%%/cryocmos/pmos_test.sp
+%%PORTDOCS%%%%EXAMPLESDIR%%/cryocmos/ringosc_meas.dat
+%%PORTDOCS%%%%EXAMPLESDIR%%/cryocmos/ringosc_test.out
+%%PORTDOCS%%%%EXAMPLESDIR%%/cryocmos/ringosc_test.sp
+%%PORTDOCS%%%%EXAMPLESDIR%%/josephson/ex8.cir
+%%PORTDOCS%%%%EXAMPLESDIR%%/josephson/exjjintr.cir
+%%PORTDOCS%%%%EXAMPLESDIR%%/josephson/exjjiv.cir
+%%PORTDOCS%%%%EXAMPLESDIR%%/josephson/intr
+%%PORTDOCS%%%%EXAMPLESDIR%%/josephson/jjcntr.cir
+%%PORTDOCS%%%%EXAMPLESDIR%%/josephson/jjoprng
+%%PORTDOCS%%%%EXAMPLESDIR%%/josephson/jtl
+%%PORTDOCS%%%%EXAMPLESDIR%%/josephson/jtl1
+%%PORTDOCS%%%%EXAMPLESDIR%%/josephson/mvtltest
+%%PORTDOCS%%%%EXAMPLESDIR%%/josephson/shutop
+%%PORTDOCS%%%%EXAMPLESDIR%%/josephson/shuttle.cir
+%%PORTDOCS%%%%EXAMPLESDIR%%/josephson/shuttlea.cir
+%%PORTDOCS%%%%EXAMPLESDIR%%/josephson/strange
+%%PORTDOCS%%%%EXAMPLESDIR%%/josephson/thcntr
+%%PORTDOCS%%%%EXAMPLESDIR%%/josephson/theta
+%%PORTDOCS%%@dirrm %%EXAMPLESDIR%%/cryocmos
+%%PORTDOCS%%@dirrm %%EXAMPLESDIR%%/josephson
+%%PORTDOCS%%@dirrm %%EXAMPLESDIR%%