Two more patches to get a GNU program to compile with a GNU compiler.

2 files changed, 69 insertions, 0 deletions

diff --git a/devel/i386-rtems-gdb/files/patch-sim::ppc::gen-idecode.c b/devel/i386-rtems-gdb/files/patch-sim::ppc::gen-idecode.c
new file mode 100644
index 000000000000..fc0c12f18cca
--- /dev/null
+++ b/devel/i386-rtems-gdb/files/patch-sim::ppc::gen-idecode.c
@@ -0,0 +1,58 @@
+--- sim/ppc/gen-idecode.c.orig	Fri Feb 20 17:00:10 2004
++++ sim/ppc/gen-idecode.c	Fri Feb 20 17:00:57 2004
+@@ -757,21 +757,21 @@
+ 
+   if (!generate_smp) {
+ 
+-    lf_putstr(file, "
+-/* CASE 1: NO SMP (with or with out instruction cache).
+-
+-   In this case, we can take advantage of the fact that the current
+-   instruction address does not need to be returned to the cpu object
+-   after every execution of an instruction.  Instead it only needs to
+-   be saved when either A. the main loop exits or B. A cpu-halt or
+-   cpu-restart call forces the loop to be re-enered.  The later
+-   functions always save the current cpu instruction address.
+-
+-   Two subcases also exist that with and that without an instruction
+-   cache.
+-
+-   An additional complexity is the need to ensure that a 1:1 ratio
+-   is maintained between the execution of an instruction and the
++    lf_putstr(file, "\
++/* CASE 1: NO SMP (with or with out instruction cache).\
++\
++   In this case, we can take advantage of the fact that the current\
++   instruction address does not need to be returned to the cpu object\
++   after every execution of an instruction.  Instead it only needs to\
++   be saved when either A. the main loop exits or B. A cpu-halt or\
++   cpu-restart call forces the loop to be re-enered.  The later\
++   functions always save the current cpu instruction address.\
++\
++   Two subcases also exist that with and that without an instruction\
++   cache.\
++\
++   An additional complexity is the need to ensure that a 1:1 ratio\
++   is maintained between the execution of an instruction and the\
+    incrementing of the simulation clock */");
+ 
+     lf_putstr(file, "\n");
+@@ -867,12 +867,12 @@
+     
+   if (generate_smp) {
+ 
+-    lf_putstr(file, "
+-/* CASE 2: SMP (With or without ICACHE)
+-
+-   The complexity here comes from needing to correctly restart the
+-   system when it is aborted.  In particular if cpu0 requests a
+-   restart, the next cpu is still cpu1.  Cpu0 being restarted after
++    lf_putstr(file, "\
++/* CASE 2: SMP (With or without ICACHE)\
++\
++   The complexity here comes from needing to correctly restart the\
++   system when it is aborted.  In particular if cpu0 requests a\
++   restart, the next cpu is still cpu1.  Cpu0 being restarted after\
+    all the other CPU's and the event queue have been processed */");
+ 
+     lf_putstr(file, "\n");
diff --git a/devel/i386-rtems-gdb/files/patch-sim::ppc::gen-model.c b/devel/i386-rtems-gdb/files/patch-sim::ppc::gen-model.c
new file mode 100644
index 000000000000..7c1b25254a8c
--- /dev/null
+++ b/devel/i386-rtems-gdb/files/patch-sim::ppc::gen-model.c
@@ -0,0 +1,11 @@
+--- sim/ppc/gen-model.c.orig	Fri Feb 20 17:15:51 2004
++++ sim/ppc/gen-model.c	Fri Feb 20 17:18:16 2004
+@@ -377,7 +377,7 @@
+     lf_printf(file, "    }\n");
+     lf_printf(file, "  }\n");
+     lf_printf(file, "\n");
+-    lf_printf(file, "  error(\"Unknown model '%%s', Models which are known are:%%s\n\",\n");
++    lf_printf(file, "  error(\"Unknown model '%%s', Models which are known are:%%s\",\n");
+     lf_printf(file, "        name,\n");
+     lf_printf(file, "        \"");
+     for(model_ptr = models; model_ptr; model_ptr = model_ptr->next) {