diff options
author | araujo <araujo@FreeBSD.org> | 2012-02-06 12:37:39 +0800 |
---|---|---|
committer | araujo <araujo@FreeBSD.org> | 2012-02-06 12:37:39 +0800 |
commit | 70c61bbcd781939277316709a460c825699206a6 (patch) | |
tree | 43cc846ce890d9805ca3a3e55a8425b1356c6bd7 /devel | |
parent | e7addcaaaa3ea93d7bb45327ee8c06409526000b (diff) | |
download | freebsd-ports-gnome-70c61bbcd781939277316709a460c825699206a6.tar.gz freebsd-ports-gnome-70c61bbcd781939277316709a460c825699206a6.tar.zst freebsd-ports-gnome-70c61bbcd781939277316709a460c825699206a6.zip |
- Update to 4.6.2.
Submitted by: Tassilo Philipp <tphilipp@potion-studios.com> (maintainer via email)
Diffstat (limited to 'devel')
19 files changed, 1534 insertions, 1062 deletions
diff --git a/devel/psptoolchain-gcc-stage1/Makefile b/devel/psptoolchain-gcc-stage1/Makefile index 0286f4bd5ac1..f9ca050f40a3 100644 --- a/devel/psptoolchain-gcc-stage1/Makefile +++ b/devel/psptoolchain-gcc-stage1/Makefile @@ -6,7 +6,7 @@ # PORTNAME= gcc -PORTVERSION= 4.1.0 +PORTVERSION= 4.6.2 CATEGORIES= devel MASTER_SITES= ${MASTER_SITE_GCC} MASTER_SITE_SUBDIR= releases/${DISTNAME}/ @@ -20,11 +20,14 @@ ONLY_FOR_ARCHS= amd64 i386 PSP_GCC_STAGE_PREFIX= psp/stage1 +LIB_DEPENDS= gmp.10:${PORTSDIR}/math/gmp \ + mpfr.4:${PORTSDIR}/math/mpfr \ + mpc.2:${PORTSDIR}/math/mpc + BUILD_DEPENDS+= psp-addr2line:${PORTSDIR}/devel/psptoolchain-binutils \ psp-ar:${PORTSDIR}/devel/psptoolchain-binutils \ psp-as:${PORTSDIR}/devel/psptoolchain-binutils \ psp-c++filt:${PORTSDIR}/devel/psptoolchain-binutils \ - psp-gprof:${PORTSDIR}/devel/psptoolchain-binutils \ psp-ld:${PORTSDIR}/devel/psptoolchain-binutils \ psp-nm:${PORTSDIR}/devel/psptoolchain-binutils \ psp-objcopy:${PORTSDIR}/devel/psptoolchain-binutils \ @@ -37,32 +40,54 @@ BUILD_DEPENDS+= psp-addr2line:${PORTSDIR}/devel/psptoolchain-binutils \ USE_BZIP2= yes USE_GMAKE= yes +MAKE_JOBS_SAFE= yes -HAS_CONFIGURE= yes -MAKE_ENV+= PATH=${PREFIX}/${PSP_GCC_STAGE_PREFIX}/bin:${PATH} -CONFIGURE_ARGS?= --prefix=${PREFIX}/${PSP_GCC_STAGE_PREFIX} --target="psp" --enable-languages="c" --with-newlib --without-headers --disable-libssp --disable-nls --with-as=`which psp-as` --with-ld=`which psp-ld` +PATCH_WRKSRC= ${SRCDIR} +CONFIGURE_SCRIPT= ../${SRCDIR:S/${WRKDIR}\///}/configure -# Don't install documentation for psptoolchain's gcc stage 1 - makes no sense. -.if ${PKGNAMESUFFIX} == "-stage1" +SRCDIR= ${WRKDIR}/${PORTNAME}-${PORTVERSION} +WRKSRC= ${WRKDIR}/build -post-patch: - @${REINPLACE_CMD} -E 's/^(install-info:)(.*)/\1#\2/' ${WRKSRC}/gcc/Makefile.in - @${REINPLACE_CMD} -E 's/^(install-man:)(.*)/\1#\2/' ${WRKSRC}/gcc/Makefile.in - @${REINPLACE_CMD} -E 's/^(install:)(.*)/\1#\2/' ${WRKSRC}/libiberty/Makefile.in +MAKE_ENV+= PATH=${LOCALBASE}/${PSP_GCC_STAGE_PREFIX}/bin:${PREFIX}/bin:${PATH} +HAS_CONFIGURE= yes +CONFIGURE_ARGS?= --prefix=${PREFIX}/${PSP_GCC_STAGE_PREFIX} \ + --target="psp" \ + --enable-languages="c" \ + --enable-lto \ + --with-newlib \ + --with-gmp=${LOCALBASE} \ + --with-mpfr \ + --without-headers \ + --disable-libssp \ + --disable-nls \ + --with-ld=${LOCALBASE}/bin/psp-ld \ + --with-as=${LOCALBASE}/bin/psp-as \ + --mandir=${PREFIX}/man -.else +pre-configure: + @${MKDIR} ${CONFIGURE_WRKSRC} -# Disable installation of .info files and libiberty. +# Don't install any documentation for psptoolchain's gcc stage 1 - makes no sense. +# Disable installation of .info files and libiberty for both stages. post-patch: - @${REINPLACE_CMD} -E 's/^(install-info:)(.*)/\1#\2/' ${WRKSRC}/gcc/Makefile.in - @${REINPLACE_CMD} -E 's/^(install:)(.*)/\1#\2/' ${WRKSRC}/libiberty/Makefile.in + @${REINPLACE_CMD} -E "s/^(install-data-am:)(.*)install-info-am(.*)/\1 \2 \3/" \ + ${SRCDIR}/libquadmath/Makefile.in + @${REINPLACE_CMD} -E "s/^(install:)(.*)/\1#\2/" ${SRCDIR}/libiberty/Makefile.in + @${REINPLACE_CMD} -E \ + -e "/^ \\$$\(mkinstalldirs\) \\$$\(DESTDIR\)\\$$\((infodir|man7dir)\)/d" \ + -e "s/^(install-info:)(.*)/\1#\2/" \ + -e "/^ \\$$\(DESTDIR\)\\$$\(man7dir\)\/(fsf-funding|gfdl|gpl)\\$$\(man7ext\)/d" \ + ${SRCDIR}/gcc/Makefile.in +.if ${PKGNAMESUFFIX} == "-stage1" + @${REINPLACE_CMD} -E "s/^(install-man:)(.*)/\1#\2/" ${SRCDIR}/gcc/Makefile.in +.endif + +# Stage 2 installs (1) man pages. +.if ${PKGNAMESUFFIX} != "-stage1" MAN1+= psp-cpp.1 \ psp-gcc.1 \ psp-gcov.1 -MAN7= fsf-funding.7 \ - gfdl.7 \ - gpl.7 .endif diff --git a/devel/psptoolchain-gcc-stage1/distinfo b/devel/psptoolchain-gcc-stage1/distinfo index 33e7475d4837..b33a1a24d046 100644 --- a/devel/psptoolchain-gcc-stage1/distinfo +++ b/devel/psptoolchain-gcc-stage1/distinfo @@ -1,2 +1,2 @@ -SHA256 (gcc-4.1.0.tar.bz2) = 1159457a0e4c054b709547ae21ff624aebab2033e0d9e5bf46c9cf88b1970606 -SIZE (gcc-4.1.0.tar.bz2) = 38639061 +SHA256 (gcc-4.6.2.tar.bz2) = 60b05463dfe18d40d68fb8a71b25b408a01f86cc6ceaf5e6b22238b6b0f450c2 +SIZE (gcc-4.6.2.tar.bz2) = 71995338 diff --git a/devel/psptoolchain-gcc-stage1/files/patch-config.sub b/devel/psptoolchain-gcc-stage1/files/patch-config.sub index e59e912a62f4..fcd2e83d471e 100644 --- a/devel/psptoolchain-gcc-stage1/files/patch-config.sub +++ b/devel/psptoolchain-gcc-stage1/files/patch-config.sub @@ -1,14 +1,14 @@ ---- config.sub.orig 2005-12-16 12:57:40.000000000 +0000 -+++ config.sub 2006-05-07 13:27:40.000000000 +0100 -@@ -264,6 +264,7 @@ +--- ./config.sub.orig 2010-05-25 13:22:07.000000000 +0000 ++++ ./config.sub 2012-01-21 14:11:18.000000000 +0000 +@@ -279,6 +279,7 @@ | mipsisa64sb1 | mipsisa64sb1el \ | mipsisa64sr71k | mipsisa64sr71kel \ | mipstx39 | mipstx39el \ + | mipsallegrex | mipsallegrexel \ | mn10200 | mn10300 \ + | moxie \ | mt \ - | msp430 \ -@@ -346,6 +347,7 @@ +@@ -375,6 +376,7 @@ | mipsisa64sb1-* | mipsisa64sb1el-* \ | mipsisa64sr71k-* | mipsisa64sr71kel-* \ | mipstx39-* | mipstx39el-* \ @@ -16,7 +16,7 @@ | mmix-* \ | mt-* \ | msp430-* \ -@@ -689,6 +691,10 @@ +@@ -771,6 +773,10 @@ basic_machine=m68k-atari os=-mint ;; diff --git a/devel/psptoolchain-gcc-stage1/files/patch-gcc-c-incpath.c b/devel/psptoolchain-gcc-stage1/files/patch-gcc-c-incpath.c deleted file mode 100644 index 71d7ec4fa8dd..000000000000 --- a/devel/psptoolchain-gcc-stage1/files/patch-gcc-c-incpath.c +++ /dev/null @@ -1,28 +0,0 @@ ---- gcc/c-incpath.c.orig 2005-06-25 03:02:01.000000000 +0100 -+++ gcc/c-incpath.c 2006-05-07 13:27:40.000000000 +0100 -@@ -331,13 +331,18 @@ - cpp_dir *p; - - #if defined (HAVE_DOS_BASED_FILE_SYSTEM) -- /* Convert all backslashes to slashes. The native CRT stat() -- function does not recognize a directory that ends in a backslash -- (unless it is a drive root dir, such "c:\"). Forward slashes, -- trailing or otherwise, cause no problems for stat(). */ -- char* c; -- for (c = path; *c; c++) -- if (*c == '\\') *c = '/'; -+ /* Remove unnecessary trailing slashes. On some versions of MS -+ Windows, trailing _forward_ slashes cause no problems for stat(). -+ On newer versions, stat() does not recognise a directory that ends -+ in a '\\' or '/', unless it is a drive root dir, such as "c:/", -+ where it is obligatory. */ -+ int pathlen = strlen (path); -+ char* end = path + pathlen - 1; -+ /* Preserve the lead '/' or lead "c:/". */ -+ char* start = path + (pathlen > 2 && path[1] == ':' ? 3 : 1); -+ -+ for (; end > start && IS_DIR_SEPARATOR (*end); end--) -+ *end = 0; - #endif - - p = xmalloc (sizeof (cpp_dir)); diff --git a/devel/psptoolchain-gcc-stage1/files/patch-gcc-config-mips-allegrex.md b/devel/psptoolchain-gcc-stage1/files/patch-gcc-config-mips-allegrex.md index 55c789359831..d04ffe9788e9 100644 --- a/devel/psptoolchain-gcc-stage1/files/patch-gcc-config-mips-allegrex.md +++ b/devel/psptoolchain-gcc-stage1/files/patch-gcc-config-mips-allegrex.md @@ -1,6 +1,6 @@ ---- gcc/config/mips/allegrex.md.orig 1970-01-01 01:00:00.000000000 +0100 -+++ gcc/config/mips/allegrex.md 2006-05-07 13:27:40.000000000 +0100 -@@ -0,0 +1,183 @@ +--- ./gcc/config/mips/allegrex.md.orig 2012-01-21 14:11:18.000000000 +0000 ++++ ./gcc/config/mips/allegrex.md 2012-01-21 14:11:18.000000000 +0000 +@@ -0,0 +1,191 @@ +;; Sony ALLEGREX instructions. +;; Copyright (C) 2005 Free Software Foundation, Inc. +;; @@ -21,32 +21,41 @@ +;; the Free Software Foundation, 59 Temple Place - Suite 330, +;; Boston, MA 02111-1307, USA. + -+; Multiply Add and Subtract. ++(define_c_enum "unspec" [ ++ UNSPEC_WSBH ++ UNSPEC_CLO ++ UNSPEC_CTO ++ UNSPEC_CACHE ++ UNSPEC_CEIL_W_S ++ UNSPEC_FLOOR_W_S ++ UNSPEC_ROUND_W_S ++]) ++ ++;; Multiply Add and Subtract. ++;; Note: removed clobbering for madd and msub (testing needed) + +(define_insn "allegrex_madd" + [(set (match_operand:SI 0 "register_operand" "+l") -+ (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d") -+ (match_operand:SI 2 "register_operand" "d")) -+ (match_dup 0))) -+ (clobber (match_scratch:SI 3 "=h"))] ++ (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d") ++ (match_operand:SI 2 "register_operand" "d")) ++ (match_dup 0)))] + "TARGET_ALLEGREX" + "madd\t%1,%2" -+ [(set_attr "type" "imadd") -+ (set_attr "mode" "SI")]) ++ [(set_attr "type" "imadd") ++ (set_attr "mode" "SI")]) + +(define_insn "allegrex_msub" + [(set (match_operand:SI 0 "register_operand" "+l") -+ (minus:SI (match_dup 0) -+ (mult:SI (match_operand:SI 1 "register_operand" "d") -+ (match_operand:SI 2 "register_operand" "d")))) -+ (clobber (match_scratch:SI 3 "=h"))] ++ (minus:SI (match_dup 0) ++ (mult:SI (match_operand:SI 1 "register_operand" "d") ++ (match_operand:SI 2 "register_operand" "d"))))] + "TARGET_ALLEGREX" + "msub\t%1,%2" -+ [(set_attr "type" "imadd") -+ (set_attr "mode" "SI")]) ++ [(set_attr "type" "imadd") ++ (set_attr "mode" "SI")]) + + -+; Min and max. ++;; Min and max. + +(define_insn "sminsi3" + [(set (match_operand:SI 0 "register_operand" "=d") @@ -54,8 +63,8 @@ + (match_operand:SI 2 "register_operand" "d")))] + "TARGET_ALLEGREX" + "min\t%0,%1,%2" -+ [(set_attr "type" "arith") -+ (set_attr "mode" "SI")]) ++ [(set_attr "type" "arith") ++ (set_attr "mode" "SI")]) + +(define_insn "smaxsi3" + [(set (match_operand:SI 0 "register_operand" "=d") @@ -63,55 +72,54 @@ + (match_operand:SI 2 "register_operand" "d")))] + "TARGET_ALLEGREX" + "max\t%0,%1,%2" -+ [(set_attr "type" "arith") -+ (set_attr "mode" "SI")]) ++ [(set_attr "type" "arith") ++ (set_attr "mode" "SI")]) + + -+; Extended shift instructions. ++;; Extended shift instructions. + +(define_insn "allegrex_bitrev" + [(set (match_operand:SI 0 "register_operand" "=d") -+ (unspec:SI [(match_operand:SI 1 "register_operand" "d")] -+ UNSPEC_BITREV))] ++ (unspec:SI [(match_operand:SI 1 "register_operand" "d")] ++ UNSPEC_BITREV))] + "TARGET_ALLEGREX" + "bitrev\t%0,%1" -+ [(set_attr "type" "arith") -+ (set_attr "mode" "SI")]) ++ [(set_attr "type" "arith") ++ (set_attr "mode" "SI")]) + +(define_insn "allegrex_wsbh" + [(set (match_operand:SI 0 "register_operand" "=d") -+ (unspec:SI [(match_operand:SI 1 "register_operand" "d")] -+ UNSPEC_WSBH))] ++ (unspec:SI [(match_operand:SI 1 "register_operand" "d")] ++ UNSPEC_WSBH))] + "TARGET_ALLEGREX" + "wsbh\t%0,%1" -+ [(set_attr "type" "arith") -+ (set_attr "mode" "SI")]) ++ [(set_attr "type" "arith") ++ (set_attr "mode" "SI")]) + -+(define_insn "allegrex_wsbw" ++(define_insn "bswapsi2" + [(set (match_operand:SI 0 "register_operand" "=d") -+ (unspec:SI [(match_operand:SI 1 "register_operand" "d")] -+ UNSPEC_WSBW))] ++ (bswap:SI (match_operand:SI 1 "register_operand" "d")))] + "TARGET_ALLEGREX" + "wsbw\t%0,%1" -+ [(set_attr "type" "arith") -+ (set_attr "mode" "SI")]) ++ [(set_attr "type" "shift") ++ (set_attr "mode" "SI")]) + + -+; Count leading ones, count trailing zeros, and count trailing ones (clz is -+; already defined). ++;; Count leading ones, count trailing zeros, and count trailing ones (clz is ++;; already defined). + +(define_insn "allegrex_clo" + [(set (match_operand:SI 0 "register_operand" "=d") -+ (unspec:SI [(match_operand:SI 1 "register_operand" "d")] -+ UNSPEC_CLO))] ++ (unspec:SI [(match_operand:SI 1 "register_operand" "d")] ++ UNSPEC_CLO))] + "TARGET_ALLEGREX" + "clo\t%0,%1" -+ [(set_attr "type" "clz") -+ (set_attr "mode" "SI")]) ++ [(set_attr "type" "clz") ++ (set_attr "mode" "SI")]) + +(define_expand "ctzsi2" + [(set (match_operand:SI 0 "register_operand") -+ (ctz:SI (match_operand:SI 1 "register_operand")))] ++ (ctz:SI (match_operand:SI 1 "register_operand")))] + "TARGET_ALLEGREX" +{ + rtx r1; @@ -124,8 +132,8 @@ + +(define_expand "allegrex_cto" + [(set (match_operand:SI 0 "register_operand") -+ (unspec:SI [(match_operand:SI 1 "register_operand")] -+ UNSPEC_CTO))] ++ (unspec:SI [(match_operand:SI 1 "register_operand")] ++ UNSPEC_CTO))] + "TARGET_ALLEGREX" +{ + rtx r1; @@ -137,50 +145,50 @@ +}) + + -+; Misc. ++;; Misc. + +(define_insn "allegrex_sync" + [(unspec_volatile [(const_int 0)] UNSPEC_SYNC)] + "TARGET_ALLEGREX" + "sync" -+ [(set_attr "type" "unknown") -+ (set_attr "mode" "none")]) ++ [(set_attr "type" "unknown") ++ (set_attr "mode" "none")]) + +(define_insn "allegrex_cache" + [(unspec_volatile [(match_operand:SI 0 "const_int_operand" "") -+ (match_operand:SI 1 "register_operand" "d")] -+ UNSPEC_CACHE)] ++ (match_operand:SI 1 "register_operand" "d")] ++ UNSPEC_CACHE)] + "TARGET_ALLEGREX" + "cache\t%0,0(%1)" -+ [(set_attr "type" "unknown") -+ (set_attr "mode" "none")]) ++ [(set_attr "type" "unknown") ++ (set_attr "mode" "none")]) + + -+; Floating-point builtins. ++;; Floating-point builtins. + +(define_insn "allegrex_ceil_w_s" + [(set (match_operand:SI 0 "register_operand" "=f") -+ (unspec:SI [(match_operand:SF 1 "register_operand" "f")] -+ UNSPEC_CEIL_W_S))] ++ (unspec:SI [(match_operand:SF 1 "register_operand" "f")] ++ UNSPEC_CEIL_W_S))] + "TARGET_ALLEGREX" + "ceil.w.s\t%0,%1" -+ [(set_attr "type" "fcvt") -+ (set_attr "mode" "SF")]) ++ [(set_attr "type" "fcvt") ++ (set_attr "mode" "SF")]) + +(define_insn "allegrex_floor_w_s" + [(set (match_operand:SI 0 "register_operand" "=f") -+ (unspec:SI [(match_operand:SF 1 "register_operand" "f")] -+ UNSPEC_FLOOR_W_S))] ++ (unspec:SI [(match_operand:SF 1 "register_operand" "f")] ++ UNSPEC_FLOOR_W_S))] + "TARGET_ALLEGREX" + "floor.w.s\t%0,%1" -+ [(set_attr "type" "fcvt") -+ (set_attr "mode" "SF")]) ++ [(set_attr "type" "fcvt") ++ (set_attr "mode" "SF")]) + +(define_insn "allegrex_round_w_s" + [(set (match_operand:SI 0 "register_operand" "=f") -+ (unspec:SI [(match_operand:SF 1 "register_operand" "f")] -+ UNSPEC_ROUND_W_S))] ++ (unspec:SI [(match_operand:SF 1 "register_operand" "f")] ++ UNSPEC_ROUND_W_S))] + "TARGET_ALLEGREX" + "round.w.s\t%0,%1" -+ [(set_attr "type" "fcvt") -+ (set_attr "mode" "SF")]) ++ [(set_attr "type" "fcvt") ++ (set_attr "mode" "SF")]) diff --git a/devel/psptoolchain-gcc-stage1/files/patch-gcc-config-mips-mips-ftypes.def b/devel/psptoolchain-gcc-stage1/files/patch-gcc-config-mips-mips-ftypes.def new file mode 100644 index 000000000000..023994bf46d5 --- /dev/null +++ b/devel/psptoolchain-gcc-stage1/files/patch-gcc-config-mips-mips-ftypes.def @@ -0,0 +1,20 @@ +--- ./gcc/config/mips/mips-ftypes.def.orig 2009-02-20 15:20:38.000000000 +0000 ++++ ./gcc/config/mips/mips-ftypes.def 2012-01-21 14:11:18.000000000 +0000 +@@ -53,9 +53,12 @@ + + DEF_MIPS_FTYPE (2, (SI, DI, SI)) + DEF_MIPS_FTYPE (2, (SI, POINTER, SI)) ++DEF_MIPS_FTYPE (1, (SI, HI)) ++DEF_MIPS_FTYPE (1, (SI, SF)) + DEF_MIPS_FTYPE (1, (SI, SI)) + DEF_MIPS_FTYPE (2, (SI, SI, SI)) + DEF_MIPS_FTYPE (3, (SI, SI, SI, SI)) ++DEF_MIPS_FTYPE (1, (SI, QI)) + DEF_MIPS_FTYPE (1, (SI, V2HI)) + DEF_MIPS_FTYPE (2, (SI, V2HI, V2HI)) + DEF_MIPS_FTYPE (1, (SI, V4QI)) +@@ -124,3 +127,4 @@ + DEF_MIPS_FTYPE (2, (VOID, SI, SI)) + DEF_MIPS_FTYPE (2, (VOID, V2HI, V2HI)) + DEF_MIPS_FTYPE (2, (VOID, V4QI, V4QI)) ++DEF_MIPS_FTYPE (1, (VOID, VOID)) diff --git a/devel/psptoolchain-gcc-stage1/files/patch-gcc-config-mips-mips.c b/devel/psptoolchain-gcc-stage1/files/patch-gcc-config-mips-mips.c index d042c79b30ca..e52468a24f70 100644 --- a/devel/psptoolchain-gcc-stage1/files/patch-gcc-config-mips-mips.c +++ b/devel/psptoolchain-gcc-stage1/files/patch-gcc-config-mips-mips.c @@ -1,89 +1,104 @@ ---- gcc/config/mips/mips.c.orig 2005-12-09 08:15:58.000000000 +0000 -+++ gcc/config/mips/mips.c 2006-05-07 18:37:50.000000000 +0100 -@@ -179,6 +179,12 @@ - MIPS_VOID_FTYPE_V2HI_V2HI, - MIPS_VOID_FTYPE_V4QI_V4QI, - -+ /* For the Sony ALLEGREX. */ -+ MIPS_SI_FTYPE_QI, -+ MIPS_SI_FTYPE_HI, -+ MIPS_VOID_FTYPE_VOID, -+ MIPS_SI_FTYPE_SF, -+ - /* The last type. */ - MIPS_MAX_FTYPE_MAX - }; -@@ -220,6 +226,11 @@ - /* As above, but the instruction only sets a single $fcc register. */ +--- ./gcc/config/mips/mips.c.orig 2011-05-29 17:48:14.000000000 +0000 ++++ ./gcc/config/mips/mips.c 2012-01-21 14:11:18.000000000 +0000 +@@ -239,7 +239,12 @@ MIPS_BUILTIN_CMP_SINGLE, -+ /* The builtin corresponds to the ALLEGREX cache instruction. Operand 0 -+ is the function code (must be less than 32) and operand 1 is the base -+ address. */ -+ MIPS_BUILTIN_CACHE, -+ /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */ - MIPS_BUILTIN_BPOSGE32 +- MIPS_BUILTIN_BPOSGE32 ++ MIPS_BUILTIN_BPOSGE32, ++ ++ /* The builtin corresponds to the ALLEGREX cache instruction. Operand 0 ++ is the function code (must be less than 32) and operand 1 is the base ++ address. */ ++ MIPS_BUILTIN_CACHE }; -@@ -405,6 +416,7 @@ - static rtx mips_expand_builtin_compare (enum mips_builtin_type, - enum insn_code, enum mips_fp_condition, - rtx, tree); -+static rtx mips_expand_builtin_cache (enum insn_code icode, rtx, tree); - static rtx mips_expand_builtin_bposge (enum mips_builtin_type, rtx); - static void mips_encode_section_info (tree, rtx, int); -@@ -721,6 +733,7 @@ + /* Invoke MACRO (COND) for each C.cond.fmt condition. */ +@@ -516,6 +521,10 @@ + normal branch. */ + static bool mips_branch_likely; - /* MIPS II */ - { "r6000", PROCESSOR_R6000, 2 }, -+ { "allegrex", PROCESSOR_ALLEGREX, 2 }, ++/* Preferred stack boundary for proper stack vars alignment */ ++unsigned int mips_preferred_stack_boundary; ++unsigned int mips_preferred_stack_align; ++ + /* The current instruction-set architecture. */ + enum processor mips_arch; + const struct mips_cpu_info *mips_arch_info; +@@ -691,6 +700,7 @@ - /* MIPS III */ - { "r4000", PROCESSOR_R4000, 3 }, -@@ -10169,6 +10182,67 @@ - BPOSGE_BUILTIN (32, MASK_DSP) - }; + /* MIPS II processors. */ + { "r6000", PROCESSOR_R6000, 2, 0 }, ++ { "allegrex", PROCESSOR_ALLEGREX, 2, 0 }, + + /* MIPS III processors. */ + { "r4000", PROCESSOR_R4000, 3, 0 }, +@@ -969,6 +979,9 @@ + 1, /* branch_cost */ + 4 /* memory_latency */ + }, ++ { /* Allegrex */ ++ DEFAULT_COSTS ++ }, + { /* Loongson-2E */ + DEFAULT_COSTS + }, +@@ -12605,6 +12618,7 @@ + AVAIL_NON_MIPS16 (dspr2_32, !TARGET_64BIT && TARGET_DSPR2) + AVAIL_NON_MIPS16 (loongson, TARGET_LOONGSON_VECTORS) + AVAIL_NON_MIPS16 (cache, TARGET_CACHE_BUILTIN) ++AVAIL_NON_MIPS16 (allegrex, TARGET_ALLEGREX) + + /* Construct a mips_builtin_description from the given arguments. + +@@ -12701,6 +12715,30 @@ + MIPS_BUILTIN (bposge, f, "bposge" #VALUE, \ + MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL) -+/* Builtin functions for the Sony ALLEGREX processor. -+ -+ These have the `__builtin_allgrex_' prefix instead of `__builtin_mips_' -+ to maintain compatibility with Sony's ALLEGREX GCC port. -+ -+ Some of the builtins may seem redundant, but they are the same as the -+ builtins defined in the Sony compiler. I chose to map redundant and -+ trivial builtins to the original instruction instead of creating -+ duplicate patterns specifically for the ALLEGREX (as Sony does). */ -+ +/* Define a MIPS_BUILTIN_DIRECT function for instruction CODE_FOR_allegrex_<INSN>. + FUNCTION_TYPE and TARGET_FLAGS are builtin_description fields. */ -+#define DIRECT_ALLEGREX_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \ -+ { CODE_FOR_allegrex_ ## INSN, 0, "__builtin_allegrex_" #INSN, \ -+ MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, TARGET_FLAGS } ++#define DIRECT_ALLEGREX_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \ ++ { CODE_FOR_allegrex_ ## INSN, MIPS_FP_COND_f, "__builtin_allegrex_" #INSN, \ ++ MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, mips_builtin_avail_allegrex } + +/* Same as the above, but mapped to an instruction that doesn't share the + NAME. NAME is the name of the builtin without the builtin prefix. */ -+#define DIRECT_ALLEGREX_NAMED_BUILTIN(NAME, INSN, FUNCTION_TYPE, TARGET_FLAGS) \ -+ { CODE_FOR_ ## INSN, 0, "__builtin_allegrex_" #NAME, \ -+ MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, TARGET_FLAGS } ++#define DIRECT_ALLEGREX_NAMED_BUILTIN(NAME, INSN, FUNCTION_TYPE, TARGET_FLAGS) \ ++ { CODE_FOR_ ## INSN, MIPS_FP_COND_f, "__builtin_allegrex_" #NAME, \ ++ MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, mips_builtin_avail_allegrex } + +/* Define a MIPS_BUILTIN_DIRECT_NO_TARGET function for instruction + CODE_FOR_allegrex_<INSN>. FUNCTION_TYPE and TARGET_FLAGS are + builtin_description fields. */ -+#define DIRECT_ALLEGREX_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \ -+ { CODE_FOR_allegrex_ ## INSN, 0, "__builtin_allegrex_" #INSN, \ -+ MIPS_BUILTIN_DIRECT_NO_TARGET, FUNCTION_TYPE, TARGET_FLAGS } ++#define DIRECT_ALLEGREX_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \ ++ { CODE_FOR_allegrex_ ## INSN, MIPS_FP_COND_f, "__builtin_allegrex_" #INSN, \ ++ MIPS_BUILTIN_DIRECT_NO_TARGET, FUNCTION_TYPE, mips_builtin_avail_allegrex } + +/* Define a builtin with a specific function TYPE. */ -+#define SPECIAL_ALLEGREX_BUILTIN(TYPE, INSN, FUNCTION_TYPE, TARGET_FLAGS) \ -+ { CODE_FOR_allegrex_ ## INSN, 0, "__builtin_allegrex_" #INSN, \ -+ MIPS_BUILTIN_ ## TYPE, FUNCTION_TYPE, TARGET_FLAGS } ++#define SPECIAL_ALLEGREX_BUILTIN(TYPE, INSN, FUNCTION_TYPE, TARGET_FLAGS) \ ++ { CODE_FOR_allegrex_ ## INSN, MIPS_FP_COND_f, "__builtin_allegrex_" #INSN, \ ++ MIPS_BUILTIN_ ## TYPE, FUNCTION_TYPE, mips_builtin_avail_allegrex } ++ + /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME> + for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a + builtin_description field. */ +@@ -12945,6 +12983,40 @@ + DIRECT_BUILTIN (dpsqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32), + DIRECT_BUILTIN (dpsqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32), + ++/* Builtin functions for the Sony ALLEGREX processor. ++ ++ These have the `__builtin_allegrex_' prefix instead of `__builtin_mips_' ++ to maintain compatibility with Sony's ALLEGREX GCC port. ++ ++ Some of the builtins may seem redundant, but they are the same as the ++ builtins defined in the Sony compiler. I chose to map redundant and ++ trivial builtins to the original instruction instead of creating ++ duplicate patterns specifically for the ALLEGREX (as Sony does). */ + -+static const struct builtin_description allegrex_bdesc[] = -+{ + DIRECT_ALLEGREX_BUILTIN(bitrev, MIPS_SI_FTYPE_SI, 0), + DIRECT_ALLEGREX_BUILTIN(wsbh, MIPS_SI_FTYPE_SI, 0), -+ DIRECT_ALLEGREX_BUILTIN(wsbw, MIPS_SI_FTYPE_SI, 0), ++ DIRECT_ALLEGREX_NAMED_BUILTIN(wsbw, bswapsi2, MIPS_SI_FTYPE_SI, 0), + DIRECT_ALLEGREX_NAMED_BUILTIN(clz, clzsi2, MIPS_SI_FTYPE_SI, 0), + DIRECT_ALLEGREX_BUILTIN(clo, MIPS_SI_FTYPE_SI, 0), + DIRECT_ALLEGREX_NAMED_BUILTIN(ctz, ctzsi2, MIPS_SI_FTYPE_SI, 0), @@ -103,121 +118,89 @@ + DIRECT_ALLEGREX_BUILTIN(ceil_w_s, MIPS_SI_FTYPE_SF, 0), + DIRECT_ALLEGREX_BUILTIN(floor_w_s, MIPS_SI_FTYPE_SF, 0), + DIRECT_ALLEGREX_BUILTIN(round_w_s, MIPS_SI_FTYPE_SF, 0), -+ DIRECT_ALLEGREX_NAMED_BUILTIN(trunc_w_s, fix_truncsfsi2_insn, MIPS_SI_FTYPE_SF, 0) -+}; -+ - /* This helps provide a mapping from builtin function codes to bdesc - arrays. */ - -@@ -10189,6 +10263,7 @@ - { - { mips_bdesc, ARRAY_SIZE (mips_bdesc), PROCESSOR_MAX }, - { sb1_bdesc, ARRAY_SIZE (sb1_bdesc), PROCESSOR_SB1 }, -+ { allegrex_bdesc, ARRAY_SIZE (allegrex_bdesc), PROCESSOR_ALLEGREX }, - { dsp_bdesc, ARRAY_SIZE (dsp_bdesc), PROCESSOR_MAX } - }; - -@@ -10292,6 +10367,9 @@ - case MIPS_BUILTIN_BPOSGE32: - return mips_expand_builtin_bposge (type, target); - -+ case MIPS_BUILTIN_CACHE: -+ return mips_expand_builtin_cache (icode, target, arglist); -+ - default: - return 0; - } -@@ -10310,8 +10388,8 @@ - tree V4QI_type_node; - unsigned int offset; - -- /* We have only builtins for -mpaired-single, -mips3d and -mdsp. */ -- if (!TARGET_PAIRED_SINGLE_FLOAT && !TARGET_DSP) -+ /* We have only builtins for -mpaired-single, -mips3d and -mdsp and the Sony ALLEGREX. */ -+ if (!TARGET_PAIRED_SINGLE_FLOAT && !TARGET_DSP && !TARGET_ALLEGREX) - return; - - if (TARGET_PAIRED_SINGLE_FLOAT) -@@ -10376,6 +10454,44 @@ - double_type_node, double_type_node, NULL_TREE); - } - -+ if (TARGET_ALLEGREX) -+ { -+ types[MIPS_SI_FTYPE_QI] -+ = build_function_type_list (intSI_type_node, -+ intQI_type_node, -+ NULL_TREE); -+ -+ types[MIPS_SI_FTYPE_HI] -+ = build_function_type_list (intSI_type_node, -+ intHI_type_node, -+ NULL_TREE); -+ -+ types[MIPS_SI_FTYPE_SI] -+ = build_function_type_list (intSI_type_node, -+ intSI_type_node, -+ NULL_TREE); -+ -+ types[MIPS_SI_FTYPE_SI_SI] -+ = build_function_type_list (intSI_type_node, -+ intSI_type_node, intSI_type_node, -+ NULL_TREE); -+ -+ types[MIPS_VOID_FTYPE_VOID] -+ = build_function_type_list (void_type_node, void_type_node, NULL_TREE); -+ -+ types[MIPS_VOID_FTYPE_SI_SI] -+ = build_function_type_list (void_type_node, -+ intSI_type_node, intSI_type_node, NULL_TREE); -+ -+ types[MIPS_SF_FTYPE_SF] -+ = build_function_type_list (float_type_node, -+ float_type_node, NULL_TREE); -+ -+ types[MIPS_SI_FTYPE_SF] -+ = build_function_type_list (intSI_type_node, -+ float_type_node, NULL_TREE); -+ } -+ - if (TARGET_DSP) - { - V2HI_type_node = build_vector_type_for_mode (intHI_type_node, V2HImode); -@@ -10557,6 +10673,10 @@ ++ DIRECT_ALLEGREX_NAMED_BUILTIN(trunc_w_s, fix_truncsfsi2_insn, MIPS_SI_FTYPE_SF, 0), ++ + /* Builtin functions for ST Microelectronics Loongson-2E/2F cores. */ + LOONGSON_BUILTIN (packsswh, MIPS_V4HI_FTYPE_V2SI_V2SI), + LOONGSON_BUILTIN (packsshb, MIPS_V8QI_FTYPE_V4HI_V4HI), +@@ -13096,6 +13168,8 @@ + /* Standard mode-based argument types. */ + #define MIPS_ATYPE_UQI unsigned_intQI_type_node + #define MIPS_ATYPE_SI intSI_type_node ++#define MIPS_ATYPE_HI intHI_type_node ++#define MIPS_ATYPE_QI intQI_type_node + #define MIPS_ATYPE_USI unsigned_intSI_type_node + #define MIPS_ATYPE_DI intDI_type_node + #define MIPS_ATYPE_UDI unsigned_intDI_type_node +@@ -13270,6 +13344,9 @@ - switch (i) + switch (opno) { -+ case 0: -+ emit_insn (GEN_FCN (icode) (0)); -+ break; -+ ++ case 0: ++ emit_insn (GEN_FCN (icode) (0)); ++ break; case 2: emit_insn (GEN_FCN (icode) (ops[0], ops[1])); break; -@@ -10767,4 +10887,26 @@ - } +@@ -13439,6 +13516,28 @@ + const1_rtx, const0_rtx); } - + +/* Expand a __builtin_allegrex_cache() function. Make sure the passed + cache function code is less than 32. */ + +static rtx -+mips_expand_builtin_cache (enum insn_code icode, rtx target, tree arglist) ++mips_expand_builtin_cache (enum insn_code icode, rtx target, tree exp) +{ + rtx op0, op1; + -+ op0 = mips_prepare_builtin_arg (icode, 0, &arglist); -+ op1 = mips_prepare_builtin_arg (icode, 1, &arglist); ++ op0 = mips_prepare_builtin_arg (icode, 0, exp, 0); ++ op1 = mips_prepare_builtin_arg (icode, 1, exp, 1); + + if (GET_CODE (op0) == CONST_INT) + if (INTVAL (op0) < 0 || INTVAL (op0) > 0x1f) + { -+ error ("invalid function code '%d'", INTVAL (op0)); -+ return const0_rtx; ++ error ("invalid function code '%d'", INTVAL (op0)); ++ return const0_rtx; + } + + emit_insn (GEN_FCN (icode) (op0, op1)); + return target; +} -+ - #include "gt-mips.h" ++ + /* Implement TARGET_EXPAND_BUILTIN. */ + + static rtx +@@ -13484,6 +13583,9 @@ + + case MIPS_BUILTIN_BPOSGE32: + return mips_expand_builtin_bposge (d->builtin_type, target); ++ ++ case MIPS_BUILTIN_CACHE: ++ return mips_expand_builtin_cache (d->icode, target, exp); + } + gcc_unreachable (); + } +@@ -15918,6 +16020,22 @@ + Do all CPP-sensitive stuff in non-MIPS16 mode; we'll switch to + MIPS16 mode afterwards if need be. */ + mips_set_mips16_mode (false); ++ ++ /* Validate -mpreferred-stack-boundary= value, or provide default. ++ The default of 128-bit is for newABI else 64-bit. */ ++ mips_preferred_stack_boundary = (TARGET_NEWABI ? 128 : 64); ++ mips_preferred_stack_align = (TARGET_NEWABI ? 16 : 8); ++ if (mips_preferred_stack_boundary_string) ++ { ++ i = atoi (mips_preferred_stack_boundary_string); ++ if (i < 2 || i > 12) ++ error ("-mpreferred-stack-boundary=%d is not between 2 and 12", i); ++ else ++ { ++ mips_preferred_stack_align = (1 << i); ++ mips_preferred_stack_boundary = mips_preferred_stack_align * 8; ++ } ++ } + } + + /* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */ diff --git a/devel/psptoolchain-gcc-stage1/files/patch-gcc-config-mips-mips.h b/devel/psptoolchain-gcc-stage1/files/patch-gcc-config-mips-mips.h index b1f746b8ffca..ccb4f8e1a8fe 100644 --- a/devel/psptoolchain-gcc-stage1/files/patch-gcc-config-mips-mips.h +++ b/devel/psptoolchain-gcc-stage1/files/patch-gcc-config-mips-mips.h @@ -1,98 +1,104 @@ ---- gcc/config/mips/mips.h.orig 2006-02-17 21:38:59.000000000 +0000 -+++ gcc/config/mips/mips.h 2006-05-07 18:37:54.000000000 +0100 -@@ -59,6 +59,7 @@ - PROCESSOR_R9000, - PROCESSOR_SB1, - PROCESSOR_SR71000, -+ PROCESSOR_ALLEGREX, - PROCESSOR_MAX - }; - -@@ -194,6 +195,7 @@ - #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000) - #define TARGET_SB1 (mips_arch == PROCESSOR_SB1) +--- ./gcc/config/mips/mips.h.orig 2011-03-08 20:51:11.000000000 +0000 ++++ ./gcc/config/mips/mips.h 2012-01-21 14:11:18.000000000 +0000 +@@ -231,6 +231,7 @@ + #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \ + || mips_arch == PROCESSOR_SB1A) #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000) +#define TARGET_ALLEGREX (mips_arch == PROCESSOR_ALLEGREX) /* Scheduling target defines. */ - #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000) -@@ -208,6 +210,7 @@ - #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000) - #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000) - #define TUNE_SB1 (mips_tune == PROCESSOR_SB1) + #define TUNE_20KC (mips_tune == PROCESSOR_20KC) +@@ -258,6 +259,7 @@ + #define TUNE_OCTEON (mips_tune == PROCESSOR_OCTEON) + #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \ + || mips_tune == PROCESSOR_SB1A) +#define TUNE_ALLEGREX (mips_tune == PROCESSOR_ALLEGREX) - /* True if the pre-reload scheduler should try to create chains of - multiply-add or multiply-subtract instructions. For example, -@@ -578,6 +581,9 @@ - && !TARGET_MIPS5500 \ - && !TARGET_MIPS16) + /* Whether vector modes and intrinsics for ST Microelectronics + Loongson-2E/2F processors should be enabled. In o32 pairs of +@@ -852,6 +854,9 @@ + /* ISA has LDC1 and SDC1. */ + #define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 && !TARGET_MIPS16) +/* ISA has just the integer condition move instructions (movn,movz) */ -+#define ISA_HAS_INT_CONDMOVE (TARGET_ALLEGREX) ++#define ISA_HAS_INT_CONDMOVE (TARGET_ALLEGREX) + /* ISA has the mips4 FP condition code instructions: FP-compare to CC, branch on CC, and move (both FP and non-FP) on CC. */ #define ISA_HAS_8CC (ISA_MIPS4 \ -@@ -594,7 +600,8 @@ +@@ -874,6 +879,7 @@ /* ISA has conditional trap instructions. */ #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \ -- && !TARGET_MIPS16) -+ && !TARGET_MIPS16 \ -+ && !TARGET_ALLEGREX) ++ && !TARGET_ALLEGREX \ + && !TARGET_MIPS16) /* ISA has integer multiply-accumulate instructions, madd and msub. */ - #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \ -@@ -612,6 +619,7 @@ - #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \ - || ISA_MIPS32R2 \ - || ISA_MIPS64 \ -+ || TARGET_ALLEGREX \ - ) && !TARGET_MIPS16) +@@ -910,6 +916,7 @@ + /* ISA has count leading zeroes/ones instruction (not implemented). */ + #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \ + || ISA_MIPS32R2 \ ++ || TARGET_ALLEGREX \ + || ISA_MIPS64 \ + || ISA_MIPS64R2) \ + && !TARGET_MIPS16) +@@ -955,6 +962,7 @@ + || TARGET_MIPS5400 \ + || TARGET_MIPS5500 \ + || TARGET_SR71K \ ++ || TARGET_ALLEGREX \ + || TARGET_SMARTMIPS) \ + && !TARGET_MIPS16) - /* ISA has double-word count leading zeroes/ones instruction (not -@@ -659,6 +667,7 @@ - || TARGET_MIPS5400 \ - || TARGET_MIPS5500 \ - || TARGET_SR71K \ -+ || TARGET_ALLEGREX \ - )) +@@ -984,11 +992,13 @@ - /* ISA has 64-bit rotate right instruction. */ -@@ -692,11 +701,13 @@ /* ISA includes the MIPS32r2 seb and seh instructions. */ - #define ISA_HAS_SEB_SEH (!TARGET_MIPS16 \ - && (ISA_MIPS32R2 \ -+ || TARGET_ALLEGREX \ - )) + #define ISA_HAS_SEB_SEH ((ISA_MIPS32R2 \ ++ || TARGET_ALLEGREX \ + || ISA_MIPS64R2) \ + && !TARGET_MIPS16) /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */ - #define ISA_HAS_EXT_INS (!TARGET_MIPS16 \ - && (ISA_MIPS32R2 \ -+ || TARGET_ALLEGREX \ - )) + #define ISA_HAS_EXT_INS ((ISA_MIPS32R2 \ ++ || TARGET_ALLEGREX \ + || ISA_MIPS64R2) \ + && !TARGET_MIPS16) - /* True if the result of a load is not available to the next instruction. -@@ -727,7 +738,8 @@ - #define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \ - || ISA_MIPS32R2 \ +@@ -1038,7 +1048,8 @@ || ISA_MIPS64 \ -- || TARGET_MIPS5500) -+ || TARGET_MIPS5500 \ + || ISA_MIPS64R2 \ + || TARGET_MIPS5500 \ +- || TARGET_LOONGSON_2EF) ++ || TARGET_LOONGSON_2EF \ + || TARGET_ALLEGREX) + + /* ISA includes synci, jr.hb and jalr.hb. */ + #define ISA_HAS_SYNCI ((ISA_MIPS32R2 \ +@@ -2133,7 +2144,7 @@ + `crtl->outgoing_args_size'. */ + #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1 + +-#define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64) ++#define STACK_BOUNDARY (mips_preferred_stack_boundary) - /* Add -G xx support. */ + /* Symbolic macros for the registers used to return integer and floating + point values. */ +@@ -2259,7 +2270,7 @@ + /* Treat LOC as a byte offset from the stack pointer and round it up + to the next fully-aligned offset. */ + #define MIPS_STACK_ALIGN(LOC) \ +- (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8) ++ (((LOC) + (mips_preferred_stack_align - 1)) & -(mips_preferred_stack_align)) -@@ -1143,6 +1155,11 @@ - #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ - ((VALUE) = GET_MODE_BITSIZE (MODE), true) -+/* The [d]clz instructions have the natural values at 0. */ -+ -+#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ -+ ((VALUE) = GET_MODE_BITSIZE (MODE), true) -+ - /* Standard register usage. */ + /* Output assembler code to FILE to increment profiler label # LABELNO +@@ -2911,6 +2922,9 @@ + #endif + #endif - /* Number of hardware registers. We have: ++extern unsigned int mips_preferred_stack_boundary; ++extern unsigned int mips_preferred_stack_align; ++ + #ifndef HAVE_AS_TLS + #define HAVE_AS_TLS 0 + #endif diff --git a/devel/psptoolchain-gcc-stage1/files/patch-gcc-config-mips-mips.md b/devel/psptoolchain-gcc-stage1/files/patch-gcc-config-mips-mips.md index 08bbc397d660..251de16291d8 100644 --- a/devel/psptoolchain-gcc-stage1/files/patch-gcc-config-mips-mips.md +++ b/devel/psptoolchain-gcc-stage1/files/patch-gcc-config-mips-mips.md @@ -1,70 +1,69 @@ ---- gcc/config/mips/mips.md.orig 2005-07-29 18:25:27.000000000 +0100 -+++ gcc/config/mips/mips.md 2006-05-07 14:59:33.000000000 +0100 -@@ -142,6 +142,21 @@ - (UNSPEC_MTHLIP 365) - (UNSPEC_WRDSP 366) - (UNSPEC_RDDSP 367) -+ -+ ;; Sony ALLEGREX instructions -+ (UNSPEC_WSBH 401) -+ (UNSPEC_WSBW 402) -+ -+ (UNSPEC_CLO 403) -+ (UNSPEC_CTO 404) -+ -+ (UNSPEC_CACHE 405) -+ (UNSPEC_SYNC 406) -+ -+ (UNSPEC_CEIL_W_S 407) -+ (UNSPEC_FLOOR_W_S 408) -+ (UNSPEC_ROUND_W_S 409) -+ - ] - ) +--- ./gcc/config/mips/mips.md.orig 2011-03-03 21:56:58.000000000 +0000 ++++ ./gcc/config/mips/mips.md 2012-01-21 14:11:19.000000000 +0000 +@@ -37,6 +37,7 @@ + 74kf2_1 + 74kf1_1 + 74kf3_2 ++ allegrex + loongson_2e + loongson_2f + loongson_3a +@@ -598,7 +599,7 @@ + ;; This mode iterator allows :MOVECC to be used anywhere that a + ;; conditional-move-type condition is needed. + (define_mode_iterator MOVECC [SI (DI "TARGET_64BIT") +- (CC "TARGET_HARD_FLOAT && !TARGET_LOONGSON_2EF")]) ++ (CC "TARGET_HARD_FLOAT && !TARGET_LOONGSON_2EF && !TARGET_ALLEGREX")]) -@@ -1601,9 +1616,9 @@ + ;; 32-bit integer moves for which we provide move patterns. + (define_mode_iterator IMOVE32 +@@ -1885,11 +1886,11 @@ (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d")) (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))] -- "!TARGET_64BIT && ISA_HAS_MSAC" -+ "!TARGET_64BIT && (ISA_HAS_MSAC || TARGET_ALLEGREX)" +- "!TARGET_64BIT && (ISA_HAS_MSAC || GENERATE_MADD_MSUB || ISA_HAS_DSP)" ++ "!TARGET_64BIT && (ISA_HAS_MSAC || GENERATE_MADD_MSUB || ISA_HAS_DSP || TARGET_ALLEGREX)" { -- if (TARGET_MIPS5500) -+ if (TARGET_MIPS5500 || TARGET_ALLEGREX) + if (ISA_HAS_DSP_MULT) + return "msub<u>\t%q0,%1,%2"; +- else if (TARGET_MIPS5500 || GENERATE_MADD_MSUB) ++ else if (TARGET_MIPS5500 || GENERATE_MADD_MSUB || TARGET_ALLEGREX) return "msub<u>\t%1,%2"; else return "msac<u>\t$0,%1,%2"; -@@ -1718,12 +1733,12 @@ +@@ -2066,14 +2067,14 @@ (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d")) (any_extend:DI (match_operand:SI 2 "register_operand" "d"))) (match_operand:DI 3 "register_operand" "0")))] -- "(TARGET_MAD || ISA_HAS_MACC) -+ "(TARGET_MAD || ISA_HAS_MACC || TARGET_ALLEGREX) +- "(TARGET_MAD || ISA_HAS_MACC || GENERATE_MADD_MSUB || ISA_HAS_DSP) ++ "(TARGET_MAD || ISA_HAS_MACC || GENERATE_MADD_MSUB || ISA_HAS_DSP || TARGET_ALLEGREX) && !TARGET_64BIT" { if (TARGET_MAD) return "mad<u>\t%1,%2"; -- else if (TARGET_MIPS5500) -+ else if (TARGET_MIPS5500 || TARGET_ALLEGREX) + else if (ISA_HAS_DSP_MULT) + return "madd<u>\t%q0,%1,%2"; +- else if (GENERATE_MADD_MSUB || TARGET_MIPS5500) ++ else if (GENERATE_MADD_MSUB || TARGET_MIPS5500 || TARGET_ALLEGREX) return "madd<u>\t%1,%2"; else /* See comment in *macc. */ -@@ -1995,6 +2010,32 @@ +@@ -2500,6 +2501,33 @@ ;; ;; .................... ;; -+;; FIND FIRST BIT INSTRUCTION ++;; FIND FIRST BIT INSTRUCTION +;; +;; .................... +;; + +(define_expand "ffs<mode>2" + [(set (match_operand:GPR 0 "register_operand" "") -+ (ffs:GPR (match_operand:GPR 1 "register_operand" "")))] ++ (ffs:GPR (match_operand:GPR 1 "register_operand" "")))] + "ISA_HAS_CLZ_CLO" +{ + rtx r1, r2, r3, r4; -+ ++ + r1 = gen_reg_rtx (<MODE>mode); + r2 = gen_reg_rtx (<MODE>mode); + r3 = gen_reg_rtx (<MODE>mode); @@ -76,21 +75,22 @@ + emit_insn (gen_sub<mode>3 (operands[0], r4, r3)); + DONE; +}) ++ +;; +;; .................... +;; ;; NEGATION and ONE'S COMPLEMENT ;; ;; .................... -@@ -4193,6 +4234,25 @@ - [(set_attr "type" "shift") +@@ -2550,6 +2578,25 @@ + [(set_attr "alu_type" "not") (set_attr "mode" "<MODE>")]) +(define_expand "rotl<mode>3" + [(set (match_operand:GPR 0 "register_operand") -+ (rotate:GPR (match_operand:GPR 1 "register_operand") -+ (match_operand:SI 2 "arith_operand")))] -+ "ISA_HAS_ROTR_<MODE>" ++ (rotate:GPR (match_operand:GPR 1 "register_operand") ++ (match_operand:SI 2 "arith_operand")))] ++ "ISA_HAS_ROR" +{ + rtx temp; + @@ -108,7 +108,7 @@ ;; ;; .................... ;; -@@ -5306,7 +5366,7 @@ +@@ -6301,7 +6348,7 @@ (const_int 0)]) (match_operand:GPR 2 "reg_or_0_operand" "dJ,0") (match_operand:GPR 3 "reg_or_0_operand" "0,dJ")))] @@ -117,7 +117,7 @@ "@ mov%T4\t%0,%z2,%1 mov%t4\t%0,%z3,%1" -@@ -5336,8 +5396,12 @@ +@@ -6331,8 +6378,12 @@ (if_then_else:GPR (match_dup 5) (match_operand:GPR 2 "reg_or_0_operand") (match_operand:GPR 3 "reg_or_0_operand")))] @@ -125,16 +125,19 @@ + "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE" { + if (ISA_HAS_INT_CONDMOVE -+ && GET_MODE_CLASS (GET_MODE (cmp_operands[0])) == MODE_FLOAT) ++ && GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_FLOAT) + FAIL; + - gen_conditional_move (operands); + mips_expand_conditional_move (operands); DONE; }) -@@ -5428,3 +5492,6 @@ - ; The MIPS DSP Instructions. +@@ -6481,6 +6532,9 @@ + ; ST-Microelectronics Loongson-2E/2F-specific patterns. + (include "loongson.md") - (include "mips-dsp.md") -+ +; Sony ALLEGREX instructions. +(include "allegrex.md") ++ + (define_c_enum "unspec" [ + UNSPEC_ADDRESS_FIRST + ]) diff --git a/devel/psptoolchain-gcc-stage1/files/patch-gcc-config-mips-mips.opt b/devel/psptoolchain-gcc-stage1/files/patch-gcc-config-mips-mips.opt new file mode 100644 index 000000000000..dd588a83539a --- /dev/null +++ b/devel/psptoolchain-gcc-stage1/files/patch-gcc-config-mips-mips.opt @@ -0,0 +1,12 @@ +--- ./gcc/config/mips/mips.opt.orig 2011-02-17 01:59:04.000000000 +0000 ++++ ./gcc/config/mips/mips.opt 2012-01-21 14:11:19.000000000 +0000 +@@ -306,5 +306,9 @@ + Target Report Var(TARGET_XGOT) + Lift restrictions on GOT size + ++mpreferred-stack-boundary= ++Target RejectNegative Joined Var(mips_preferred_stack_boundary_string) ++Attempt to keep stack aligned to this power of 2 ++ + noasmopt + Driver diff --git a/devel/psptoolchain-gcc-stage1/files/patch-gcc-config-mips-psp.h b/devel/psptoolchain-gcc-stage1/files/patch-gcc-config-mips-psp.h index 346633c951a7..bf29a5b1439d 100644 --- a/devel/psptoolchain-gcc-stage1/files/patch-gcc-config-mips-psp.h +++ b/devel/psptoolchain-gcc-stage1/files/patch-gcc-config-mips-psp.h @@ -1,5 +1,5 @@ ---- gcc/config/mips/psp.h.orig 1970-01-01 01:00:00.000000000 +0100 -+++ gcc/config/mips/psp.h 2006-05-07 13:27:43.000000000 +0100 +--- ./gcc/config/mips/psp.h.orig 2012-01-21 14:11:19.000000000 +0000 ++++ ./gcc/config/mips/psp.h 2012-01-21 14:11:19.000000000 +0000 @@ -0,0 +1,31 @@ +/* Support for Sony's Playstation Portable (PSP). + Copyright (C) 2005 Free Software Foundation, Inc. diff --git a/devel/psptoolchain-gcc-stage1/files/patch-gcc-config-mips-t-allegrex b/devel/psptoolchain-gcc-stage1/files/patch-gcc-config-mips-t-allegrex index 8325a46872d8..7c6203b79c83 100644 --- a/devel/psptoolchain-gcc-stage1/files/patch-gcc-config-mips-t-allegrex +++ b/devel/psptoolchain-gcc-stage1/files/patch-gcc-config-mips-t-allegrex @@ -1,5 +1,5 @@ ---- gcc/config/mips/t-allegrex.orig 1970-01-01 01:00:00.000000000 +0100 -+++ gcc/config/mips/t-allegrex 2006-05-07 13:27:43.000000000 +0100 +--- ./gcc/config/mips/t-allegrex.orig 2012-01-21 14:11:19.000000000 +0000 ++++ ./gcc/config/mips/t-allegrex 2012-01-21 14:11:19.000000000 +0000 @@ -0,0 +1,29 @@ +# Suppress building libgcc1.a, since the MIPS compiler port is complete +# and does not need anything from libgcc1.a. diff --git a/devel/psptoolchain-gcc-stage1/files/patch-gcc-config.gcc b/devel/psptoolchain-gcc-stage1/files/patch-gcc-config.gcc index 93b13a289527..c45db6df2fc3 100644 --- a/devel/psptoolchain-gcc-stage1/files/patch-gcc-config.gcc +++ b/devel/psptoolchain-gcc-stage1/files/patch-gcc-config.gcc @@ -1,46 +1,21 @@ ---- gcc/config.gcc.orig 2006-02-06 16:07:46.000000000 +0000 -+++ gcc/config.gcc 2006-05-07 13:27:40.000000000 +0100 -@@ -406,12 +406,6 @@ - tm_defines="${tm_defines} FBSD_MAJOR=5" ;; - *-*-freebsd6 | *-*-freebsd[6].*) - tm_defines="${tm_defines} FBSD_MAJOR=6" ;; -- *-*-freebsd7 | *-*-freebsd[7].*) -- tm_defines="${tm_defines} FBSD_MAJOR=7" ;; -- *-*-freebsd8 | *-*-freebsd[8].*) -- tm_defines="${tm_defines} FBSD_MAJOR=8" ;; -- *-*-freebsd9 | *-*-freebsd[9].*) -- tm_defines="${tm_defines} FBSD_MAJOR=9" ;; - *) - echo 'Please update *-*-freebsd* in gcc/config.gcc' - exit 1 -@@ -756,11 +750,6 @@ - tmake_file=bfin/t-bfin-elf - use_collect2=no - ;; --bfin*-uclinux*) -- tm_file="${tm_file} dbxelf.h elfos.h bfin/elf.h bfin/uclinux.h" -- tmake_file=bfin/t-bfin-elf -- use_collect2=no -- ;; - bfin*-*) - tm_file="${tm_file} dbxelf.h elfos.h bfin/elf.h" - tmake_file=bfin/t-bfin -@@ -1584,6 +1573,18 @@ - tmake_file=mips/t-r3900 - use_fixproto=yes +--- ./gcc/config.gcc.orig 2011-07-22 16:44:50.000000000 +0000 ++++ ./gcc/config.gcc 2012-01-21 14:11:19.000000000 +0000 +@@ -2033,6 +2033,18 @@ + tm_file="elfos.h newlib-stdint.h ${tm_file} mips/r3900.h mips/elf.h" + tmake_file="mips/t-r3900 mips/t-libgcc-mips16" ;; +mipsallegrex-*-elf* | mipsallegrexel-*-elf*) -+ tm_file="elfos.h ${tm_file} mips/elf.h" -+ tmake_file=mips/t-allegrex -+ target_cpu_default="MASK_SINGLE_FLOAT|MASK_DIVIDE_BREAKS" -+ tm_defines="MIPS_ISA_DEFAULT=2 MIPS_CPU_STRING_DEFAULT=\\\"allegrex\\\" MIPS_ABI_DEFAULT=ABI_EABI" -+ case ${target} in -+ mipsallegrex*-psp-elf*) -+ tm_file="${tm_file} mips/psp.h" -+ ;; -+ esac -+ use_fixproto=yes -+ ;; ++ tm_file="elfos.h ${tm_file} mips/elf.h" ++ tmake_file=mips/t-allegrex ++ target_cpu_default="MASK_SINGLE_FLOAT|MASK_DIVIDE_BREAKS" ++ tm_defines="MIPS_ISA_DEFAULT=2 MIPS_CPU_STRING_DEFAULT=\\\"allegrex\\\" MIPS_ABI_DEFAULT=ABI_EABI" ++ case ${target} in ++ mipsallegrex*-psp-elf*) ++ tm_file="${tm_file} mips/psp.h" ++ ;; ++ esac ++ use_fixproto=yes ++ ;; mmix-knuth-mmixware) + tm_file="${tm_file} newlib-stdint.h" need_64bit_hwint=yes - ;; diff --git a/devel/psptoolchain-gcc-stage1/files/patch-gcc-version.c b/devel/psptoolchain-gcc-stage1/files/patch-gcc-version.c deleted file mode 100644 index de27520bf021..000000000000 --- a/devel/psptoolchain-gcc-stage1/files/patch-gcc-version.c +++ /dev/null @@ -1,20 +0,0 @@ ---- gcc/version.c.orig 2005-03-16 06:04:10.000000000 +0000 -+++ gcc/version.c 2006-05-07 13:47:56.000000000 +0100 -@@ -8,7 +8,7 @@ - in parentheses. You may also wish to include a number indicating - the revision of your modified compiler. */ - --#define VERSUFFIX "" -+#define VERSUFFIX " (PSPDEV 20060507)" - - /* This is the location of the online document giving instructions for - reporting bugs. If you distribute a modified version of GCC, -@@ -17,7 +17,7 @@ - forward us bugs reported to you, if you determine that they are - not bugs in your modifications.) */ - --const char bug_report_url[] = "<URL:http://gcc.gnu.org/bugs.html>"; -+const char bug_report_url[] = "<URL:http://wiki.pspdev.org/psp:toolchain#bugs>"; - - /* The complete version string, assembled from several pieces. - BASEVER, DATESTAMP, and DEVPHASE are defined by the Makefile. */ diff --git a/devel/psptoolchain-gcc-stage1/files/patch-libgcc-config.host b/devel/psptoolchain-gcc-stage1/files/patch-libgcc-config.host new file mode 100644 index 000000000000..eebc1e6c767d --- /dev/null +++ b/devel/psptoolchain-gcc-stage1/files/patch-libgcc-config.host @@ -0,0 +1,11 @@ +--- ./libgcc/config.host.orig 2011-03-14 06:06:23.000000000 +0000 ++++ ./libgcc/config.host 2012-01-21 14:11:19.000000000 +0000 +@@ -445,6 +445,8 @@ + ;; + mipstx39-*-elf* | mipstx39el-*-elf*) + ;; ++mips*-psp-elf) ++ ;; + mmix-knuth-mmixware) + extra_parts="crti.o crtn.o crtbegin.o crtend.o" + tmake_file="${tmake_file} ${cpu_type}/t-${cpu_type}" diff --git a/devel/psptoolchain-gcc-stage1/files/patch-libobjc-Makefile.in b/devel/psptoolchain-gcc-stage1/files/patch-libobjc-Makefile.in new file mode 100644 index 000000000000..d5cec421fca4 --- /dev/null +++ b/devel/psptoolchain-gcc-stage1/files/patch-libobjc-Makefile.in @@ -0,0 +1,11 @@ +--- ./libobjc/Makefile.in.orig 2010-12-23 11:26:14.000000000 +0000 ++++ ./libobjc/Makefile.in 2012-01-21 14:11:19.000000000 +0000 +@@ -74,7 +74,7 @@ + RANLIB = @RANLIB@ + + CC = @CC@ +-CFLAGS = @CFLAGS@ ++CFLAGS = -G 0 -G0 @CFLAGS@ + WARN_CFLAGS = -W -Wall -Wwrite-strings -Wstrict-prototypes + ALL_CFLAGS = -I. -I$(srcdir) $(CPPFLAGS) $(DEFS) $(CFLAGS) $(WARN_CFLAGS) \ + -DIN_GCC -DIN_TARGET_LIBS -fno-strict-aliasing -fexceptions diff --git a/devel/psptoolchain-gcc-stage1/pkg-plist b/devel/psptoolchain-gcc-stage1/pkg-plist index 2fabad952a07..94356921d519 100644 --- a/devel/psptoolchain-gcc-stage1/pkg-plist +++ b/devel/psptoolchain-gcc-stage1/pkg-plist @@ -1,63 +1,199 @@ -%%PSP_GCC_STAGE_PREFIX%%/libexec/gcc/psp/4.1.0/install-tools/mkheaders -%%PSP_GCC_STAGE_PREFIX%%/libexec/gcc/psp/4.1.0/install-tools/fixproto -%%PSP_GCC_STAGE_PREFIX%%/libexec/gcc/psp/4.1.0/install-tools/fixincl -%%PSP_GCC_STAGE_PREFIX%%/libexec/gcc/psp/4.1.0/install-tools/fixinc.sh -%%PSP_GCC_STAGE_PREFIX%%/libexec/gcc/psp/4.1.0/install-tools/fix-header -%%PSP_GCC_STAGE_PREFIX%%/libexec/gcc/psp/4.1.0/collect2 -%%PSP_GCC_STAGE_PREFIX%%/libexec/gcc/psp/4.1.0/cc1 -%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.1.0/libgcov.a -%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.1.0/libgcc.a -%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.1.0/install-tools/mkheaders.conf -%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.1.0/install-tools/macro_list -%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.1.0/install-tools/include/varargs.h -%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.1.0/install-tools/include/unwind.h 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+%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.6.2/plugin/include/tree-iterator.h +%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.6.2/plugin/include/tree-pass.h +%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.6.2/plugin/include/tree-ssa-alias.h +%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.6.2/plugin/include/tree-ssa-operands.h +%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.6.2/plugin/include/tree-ssa-sccvn.h +%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.6.2/plugin/include/tree.def +%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.6.2/plugin/include/tree.h +%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.6.2/plugin/include/treestruct.def +%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.6.2/plugin/include/vec.h +%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.6.2/plugin/include/vecir.h +%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.6.2/plugin/include/vecprim.h +%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.6.2/plugin/include/version.h +%%PSP_GCC_STAGE_PREFIX%%/libexec/gcc/psp/4.6.2/cc1 +%%PSP_GCC_STAGE_PREFIX%%/libexec/gcc/psp/4.6.2/collect2 +%%PSP_GCC_STAGE_PREFIX%%/libexec/gcc/psp/4.6.2/install-tools/fixinc.sh +%%PSP_GCC_STAGE_PREFIX%%/libexec/gcc/psp/4.6.2/install-tools/fixincl +%%PSP_GCC_STAGE_PREFIX%%/libexec/gcc/psp/4.6.2/install-tools/mkheaders +%%PSP_GCC_STAGE_PREFIX%%/libexec/gcc/psp/4.6.2/install-tools/mkinstalldirs +%%PSP_GCC_STAGE_PREFIX%%/libexec/gcc/psp/4.6.2/liblto_plugin.la +%%PSP_GCC_STAGE_PREFIX%%/libexec/gcc/psp/4.6.2/liblto_plugin.so +%%PSP_GCC_STAGE_PREFIX%%/libexec/gcc/psp/4.6.2/liblto_plugin.so.0 +%%PSP_GCC_STAGE_PREFIX%%/libexec/gcc/psp/4.6.2/lto-wrapper +%%PSP_GCC_STAGE_PREFIX%%/libexec/gcc/psp/4.6.2/lto1 +@dirrm %%PSP_GCC_STAGE_PREFIX%%/libexec/gcc/psp/4.6.2/install-tools +@dirrm %%PSP_GCC_STAGE_PREFIX%%/libexec/gcc/psp/4.6.2 @dirrm %%PSP_GCC_STAGE_PREFIX%%/libexec/gcc/psp @dirrm %%PSP_GCC_STAGE_PREFIX%%/libexec/gcc -@dirrm %%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.1.0/install-tools/include -@dirrm %%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.1.0/install-tools -@dirrm %%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.1.0/include -@dirrm %%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.1.0 +@dirrm %%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.6.2/install-tools/include +@dirrm %%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.6.2/install-tools +@dirrm %%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.6.2/include-fixed +@dirrm %%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.6.2/include +@dirrm %%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.6.2/plugin/include/ada/gcc-interface +@dirrm %%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.6.2/plugin/include/ada +@dirrm %%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.6.2/plugin/include/c-family +@dirrm %%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.6.2/plugin/include/config/mips +@dirrm %%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.6.2/plugin/include/config +@dirrm %%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.6.2/plugin/include/cp +@dirrm %%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.6.2/plugin/include/java +@dirrm %%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.6.2/plugin/include/objc +@dirrm %%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.6.2/plugin/include +@dirrm %%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.6.2/plugin +@dirrm %%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.6.2 @dirrm %%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp @dirrm %%PSP_GCC_STAGE_PREFIX%%/lib/gcc +@dirrmtry %%PSP_GCC_STAGE_PREFIX%%/share/info +@dirrmtry %%PSP_GCC_STAGE_PREFIX%%/share @dirrmtry %%PSP_GCC_STAGE_PREFIX%%/psp/lib @dirrmtry %%PSP_GCC_STAGE_PREFIX%%/psp @dirrmtry %%PSP_GCC_STAGE_PREFIX%%/include @dirrmtry %%PSP_GCC_STAGE_PREFIX%%/lib @dirrmtry %%PSP_GCC_STAGE_PREFIX%%/libexec @dirrmtry %%PSP_GCC_STAGE_PREFIX%%/bin -@dirrmtry %%PSP_GCC_STAGE_PREFIX%%/share -@dirrmtry %%PSP_GCC_STAGE_PREFIX%%/info -@dirrmtry %%PSP_GCC_STAGE_PREFIX%%/man/man7 -@dirrmtry %%PSP_GCC_STAGE_PREFIX%%/man/man1 -@dirrmtry %%PSP_GCC_STAGE_PREFIX%%/man @dirrmtry %%PSP_GCC_STAGE_PREFIX%% +@dirrmtry psp diff --git a/devel/psptoolchain-gcc-stage2/Makefile b/devel/psptoolchain-gcc-stage2/Makefile index 427d082b3b10..06ef7c661ad7 100644 --- a/devel/psptoolchain-gcc-stage2/Makefile +++ b/devel/psptoolchain-gcc-stage2/Makefile @@ -11,10 +11,20 @@ MAINTAINER= tphilipp@potion-studios.com BUILD_DEPENDS= ${LOCALBASE}/psp/lib/libc.a:${PORTSDIR}/devel/psptoolchain-newlib -BROKEN= does not build - -MAKE_ENV= CFLAGS_FOR_TARGET="-G0" -CONFIGURE_ARGS= --prefix=${PREFIX} --target="psp" --enable-languages="c,c++" --with-newlib --enable-cxx-flags="-G0" --disable-nls +MAKE_ENV= CFLAGS_FOR_TARGET="-G0" PATH=${PREFIX}/bin:${PATH} +CONFIGURE_ARGS= --prefix=${PREFIX} \ + --target="psp" \ + --enable-languages="c,c++" \ + --enable-lto \ + --with-newlib \ + --with-gmp=${LOCALBASE} \ + --with-mpfr \ + --disable-libssp \ + --disable-nls \ + --enable-cxx-flags="-G0" \ + --with-ld=${LOCALBASE}/bin/psp-ld \ + --with-as=${LOCALBASE}/bin/psp-as \ + --mandir=${PREFIX}/man MAN1= psp-g++.1 diff --git a/devel/psptoolchain-gcc-stage2/pkg-plist b/devel/psptoolchain-gcc-stage2/pkg-plist index ff19deeb479d..69fc51a0aee7 100644 --- a/devel/psptoolchain-gcc-stage2/pkg-plist +++ b/devel/psptoolchain-gcc-stage2/pkg-plist @@ -1,557 +1,877 @@ psp/lib/libsupc++.la psp/lib/libsupc++.a psp/lib/libstdc++.la +psp/lib/libstdc++.a-gdb.py psp/lib/libstdc++.a -psp/lib/libssp_nonshared.la -psp/lib/libssp_nonshared.a -psp/lib/libssp.la -psp/lib/libssp.a -psp/bin/gcc -psp/bin/g++ -psp/bin/c++ -libexec/gcc/psp/4.1.0/install-tools/mkheaders -libexec/gcc/psp/4.1.0/install-tools/fixproto -libexec/gcc/psp/4.1.0/install-tools/fixincl -libexec/gcc/psp/4.1.0/install-tools/fixinc.sh -libexec/gcc/psp/4.1.0/install-tools/fix-header -libexec/gcc/psp/4.1.0/collect2 -libexec/gcc/psp/4.1.0/cc1plus -libexec/gcc/psp/4.1.0/cc1 -lib/gcc/psp/4.1.0/libgcov.a -lib/gcc/psp/4.1.0/libgcc.a -lib/gcc/psp/4.1.0/install-tools/mkheaders.conf -lib/gcc/psp/4.1.0/install-tools/macro_list -lib/gcc/psp/4.1.0/install-tools/include/varargs.h -lib/gcc/psp/4.1.0/install-tools/include/unwind.h -lib/gcc/psp/4.1.0/install-tools/include/stddef.h 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