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authorkwm <kwm@FreeBSD.org>2010-06-12 04:51:24 +0800
committerkwm <kwm@FreeBSD.org>2010-06-12 04:51:24 +0800
commita2c4ff5dab910e1d7054a1cd1093db44f00888af (patch)
treeca53f97b16ecf91c3d8f519216b66ab37ff12030 /security
parentf1945ebf2b26e63a93cfefdb56e134626899bb9b (diff)
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Fix the build on powerpc64. By adding CPU_ARCH detection.
And by adding some G5-specific code in mpcpucache.c to detect cacheline sizes. PR: ports/147696 Submitted by: nwhitehorn@
Diffstat (limited to 'security')
-rw-r--r--security/nss/files/patch-..::coreconf::FreeBSD.mk6
-rw-r--r--security/nss/files/patch-lib_freebl_mpi_mpcpucache.c43
2 files changed, 48 insertions, 1 deletions
diff --git a/security/nss/files/patch-..::coreconf::FreeBSD.mk b/security/nss/files/patch-..::coreconf::FreeBSD.mk
index 7722e4a95f9d..46e0c7147317 100644
--- a/security/nss/files/patch-..::coreconf::FreeBSD.mk
+++ b/security/nss/files/patch-..::coreconf::FreeBSD.mk
@@ -13,7 +13,7 @@
RANLIB = ranlib
CPU_ARCH = $(OS_TEST)
-@@ -50,7 +50,22 @@
+@@ -50,7 +50,26 @@
CPU_ARCH = x86
endif
ifeq ($(CPU_ARCH),amd64)
@@ -24,6 +24,10 @@
+ifeq ($(OS_TEST),alpha)
+CPU_ARCH = alpha
+endif
++ifeq ($(OS_TEST),powerpc64)
++CPU_ARCH = powerpc
++USE_64 = 1
++endif
+ifeq ($(OS_TEST),powerpc)
+CPU_ARCH = powerpc
+endif
diff --git a/security/nss/files/patch-lib_freebl_mpi_mpcpucache.c b/security/nss/files/patch-lib_freebl_mpi_mpcpucache.c
new file mode 100644
index 000000000000..8b7d7d1be225
--- /dev/null
+++ b/security/nss/files/patch-lib_freebl_mpi_mpcpucache.c
@@ -0,0 +1,43 @@
+--- lib/freebl/mpi/mpcpucache.c.orig 2010-06-11 22:39:33.000000000 +0200
++++ lib/freebl/mpi/mpcpucache.c 2010-06-11 22:40:20.000000000 +0200
+@@ -733,6 +733,32 @@ s_mpi_getProcessorLineSize()
+ #endif
+
+ #if defined(__ppc64__)
++
++#if defined(__FreeBSD__)
++#include <sys/stddef.h>
++#include <sys/sysctl.h>
++
++#include <machine/cpu.h>
++#include <machine/md_var.h>
++
++unsigned long
++s_mpi_getProcessorLineSize()
++{
++ static int cacheline_size = 0;
++ static int cachemib[] = { CTL_MACHDEP, CPU_CACHELINE };
++ int clen;
++
++ if (cacheline_size > 0)
++ return cacheline_size;
++
++ clen = sizeof(cacheline_size);
++ if (sysctl(cachemib, sizeof(cachemib) / sizeof(cachemib[0]),
++ &cacheline_size, &clen, NULL, 0) < 0 || !cacheline_size)
++ return 128; /* guess */
++
++ return cacheline_size;
++}
++#else
+ /*
+ * Sigh, The PPC has some really nice features to help us determine cache
+ * size, since it had lots of direct control functions to do so. The POWER
+@@ -785,6 +811,7 @@ s_mpi_getProcessorLineSize()
+ }
+ return 0;
+ }
++#endif
+
+ #define MPI_GET_PROCESSOR_LINE_SIZE_DEFINED 1
+ #endif