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-rw-r--r--cad/iverilog/Makefile9
1 files changed, 2 insertions, 7 deletions
diff --git a/cad/iverilog/Makefile b/cad/iverilog/Makefile
index 434e12e917b3..cda7640bd86e 100644
--- a/cad/iverilog/Makefile
+++ b/cad/iverilog/Makefile
@@ -1,10 +1,5 @@
-# ex:ts=8
-# New ports collection makefile for: iverilog
-# Date created: Feb 13, 2001
-# Whom: Ying-Chieh Liao <ijliao@FreeBSD.org>
-#
+# Created by: Ying-Chieh Liao <ijliao@FreeBSD.org>
# $FreeBSD$
-#
PORTNAME= iverilog
PORTVERSION= 0.9.6
@@ -19,7 +14,7 @@ COMMENT= A Verilog simulation and synthesis tool
LICENSE= GPLv2
GNU_CONFIGURE= yes
-USE_BISON= build
+USES= bison
USE_GMAKE= yes
CONFIGURE_ARGS= --disable-suffix