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-rw-r--r--cad/iverilog/Makefile2
1 files changed, 1 insertions, 1 deletions
diff --git a/cad/iverilog/Makefile b/cad/iverilog/Makefile
index 40d7f16f6b1d..59d979997eb0 100644
--- a/cad/iverilog/Makefile
+++ b/cad/iverilog/Makefile
@@ -12,7 +12,7 @@ CATEGORIES= cad
MASTER_SITES= ftp://icarus.com/pub/eda/verilog/v$(PORTVERSION)/
DISTNAME= verilog-$(PORTVERSION)
-MAINTAINER= watchman@ludd.luth.se
+MAINTAINER= watchman@ludd.ltu.se
COMMENT= A Verilog simulation and synthesis tool
USE_BISON= yes