aboutsummaryrefslogtreecommitdiffstats
path: root/cad/Makefile
Commit message (Expand)AuthorAgeFilesLines
* add iverilog, a Verilog simulation and synthesis toolijliao2001-02-131-0/+1
* SCEPTRE (System for Circuit Evaluation and Prediction of Transientgrog2001-02-111-0/+1
* Activate Electric.sada2000-07-301-0/+1
* Add PISCES, a two-dimensional device simulator which includesade2000-05-031-0/+1
* cider version 1b1steve1999-12-251-0/+1
* New port QCad, a 2D-CAD program. Uses Qt-2.tg1999-12-221-0/+1
* Change Id->FreeBSD.obrien1999-08-251-1/+1
* Activate the tkgate port.steve1999-06-071-1/+2
* Sort entries. In particular, "large", "medium", "small" sort in this order,asami1998-12-071-2/+2
* Activate geda.vanilla1998-12-061-1/+2
* Enable sis, a new circuit emulator port.ghelmer1998-07-011-1/+2
* Activate xcircuit.mph1998-05-181-1/+2
* Activate kaskade.tg1997-11-171-1/+2
* Add felt.asami1997-01-151-1/+2
* Turn on mars and lprpsobrien1996-11-251-1/+2
* Add spice.tg1996-05-231-1/+2
* Add chipmunk, convert to new format along the way.asami1995-08-251-2/+6
* Clean up subdir Makefiles. They now all look like this:asami1995-05-141-1/+2
* Alphabetize.jkh1995-01-131-2/+2
* New cad groupjkh1995-01-131-0/+5
generated by cgit (git 2.34.1) at 2025-01-04 02:21:51 +0800