aboutsummaryrefslogtreecommitdiffstats
path: root/cad/p5-Verilog-Perl
Commit message (Collapse)AuthorAgeFilesLines
* - Update to 3.316swills2012-08-282-3/+3
| | | | | PR: ports/171063 Approved by: otacilio.neto@ee.ufcg.edu.br (maintainer)
* - Get Rid MD5 supportmiwi2011-03-201-1/+0
|
* - Update to 3.251sylvio2010-07-233-7/+9
| | | | | PR: ports/148726 Submitted by: Otacilio de Araujo Ramos Neto <otacilio.neto@ee.ufcg.edu.br> (maintainer)
* - Update to 3.223pgollucci2010-01-182-4/+4
| | | | | | PR: ports/142626 Submitted by: myself (pgollucci@) Approved by: otacilio.neto@ee.ufcg.edu.br (maintainer)
* - Update to 3.222pgollucci2009-12-272-4/+4
| | | | | | PR: ports/141552 Approved by: maintainer Submitted by: myself (pgollucci@)
* - Update to 3.221miwi2009-11-043-7/+9
| | | | | PR: 140231 Submitted by: Otacílio de Araújo Ramos Neto <otacilio.neto@ee.ufcg.edu.br> (maintainer)
* - Fix compile problem with over optimization caused by -O2 flag for gcc in baseaz2009-09-151-3/+8
| | | | | | | | prior OSVERSION 700042 - Unbreak Approved by: portmgr (miwi) Feature safe: yes
* - mark BROKEN does not compilemiwi2009-09-141-0/+2
|
* Update to 2.213az2009-08-242-4/+4
| | | | | PR: ports/138081 Submitted by: tacilio.net at ee.ufcg.edu.br (maintainer)
* - Update to 2.11pgollucci2009-07-153-34/+36
| | | | | PR: ports/136485 Submitted by: otacilio.neto@ee.ufcg.edu.br (maintainer)
* - Add missing dependency (bison)garga2009-05-261-0/+1
| | | | | Reported by: QAT Pointyhat to: garga
* The Verilog-Perl library is a building point for Verilog support in the Perlgarga2009-05-264-0/+97
language. It includes: * Verilog::Getopt which parses command line options similar to C++ and VCS. * Verilog::Language which knows the language keywords and parses numbers. * Verilog::Netlist which builds netlists out of Verilog files. This allows easy scripts to determine things such as the hierarchy of modules. * Verilog::Parser invokes callbacks for language tokens. * Verilog::Preproc preprocesses the language, and allows reading post-processed files right from Perl without temporary files. * vpassert inserts PLIish warnings and assertions for any simulator. * vppreproc preprocesses the complete Verilog 2001 and SystemVerilog language. * vrename renames and cross-references Verilog symbols. Vrename creates Verilog cross references and makes it easy to rename signal and module names across multiple files. Vrename uses a simple and efficient three step process. First, you run vrename to create a list of signals in the design. You then edit this list, changing as many symbols as you wish. Vrename is then run a second time to apply the changes. WWW: http://www.veripool.org/wiki/verilog-perl PR: ports/134124 Submitted by: Otacílio de Araújo Ramos Neto <otacilio.neto at ee.ufcg.edu.br>
generated by cgit (git 2.34.1) at 2024-11-24 19:55:12 +0800