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cad)
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Submitted by: az
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PR: ports/177726
Submitted by: Otacilio <otacilio.neto@ee.ufcg.edu.br> (maintainer)
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It brings bison as a build dependency in case it is set the following way:
USES= bison or USES= bison:build
it brings bison as a run dependency in case it is set the following way:
USES= bison:run
it brings bison both as a run and build dependency in case it the set the following way:
USES= bison:both
While here trim some headers
Convert some USE_GNOME= gnomehack to USES= pathfix
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PR: ports/171063
Approved by: otacilio.neto@ee.ufcg.edu.br (maintainer)
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PR: ports/148726
Submitted by: Otacilio de Araujo Ramos Neto <otacilio.neto@ee.ufcg.edu.br> (maintainer)
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PR: ports/142626
Submitted by: myself (pgollucci@)
Approved by: otacilio.neto@ee.ufcg.edu.br (maintainer)
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PR: ports/141552
Approved by: maintainer
Submitted by: myself (pgollucci@)
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PR: 140231
Submitted by: Otacílio de Araújo Ramos Neto <otacilio.neto@ee.ufcg.edu.br> (maintainer)
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prior OSVERSION 700042
- Unbreak
Approved by: portmgr (miwi)
Feature safe: yes
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PR: ports/138081
Submitted by: tacilio.net at ee.ufcg.edu.br (maintainer)
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PR: ports/136485
Submitted by: otacilio.neto@ee.ufcg.edu.br (maintainer)
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Reported by: QAT
Pointyhat to: garga
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language. It includes:
* Verilog::Getopt which parses command line options similar to C++ and VCS.
* Verilog::Language which knows the language keywords and parses numbers.
* Verilog::Netlist which builds netlists out of Verilog files. This allows
easy scripts to determine things such as the hierarchy of modules.
* Verilog::Parser invokes callbacks for language tokens.
* Verilog::Preproc preprocesses the language, and allows reading
post-processed files right from Perl without temporary files.
* vpassert inserts PLIish warnings and assertions for any simulator.
* vppreproc preprocesses the complete Verilog 2001 and SystemVerilog language.
* vrename renames and cross-references Verilog symbols. Vrename creates Verilog
cross references and makes it easy to rename signal and module names across
multiple files. Vrename uses a simple and efficient three step process.
First, you run vrename to create a list of signals in the design. You then
edit this list, changing as many symbols as you wish. Vrename is then run a
second time to apply the changes.
WWW: http://www.veripool.org/wiki/verilog-perl
PR: ports/134124
Submitted by: Otacílio de Araújo Ramos Neto <otacilio.neto at ee.ufcg.edu.br>
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