From 2c521d37f476965fe127f976ef2eb98205423df1 Mon Sep 17 00:00:00 2001
From: ehaupt <ehaupt@FreeBSD.org>
Date: Thu, 27 Feb 2014 13:43:27 +0000
Subject: Support staging

---
 cad/gplcver/Makefile | 10 ++++------
 1 file changed, 4 insertions(+), 6 deletions(-)

(limited to 'cad/gplcver')

diff --git a/cad/gplcver/Makefile b/cad/gplcver/Makefile
index 2d3bc53f6ceb..b056f6edbfa3 100644
--- a/cad/gplcver/Makefile
+++ b/cad/gplcver/Makefile
@@ -10,17 +10,15 @@ DISTNAME=	${PORTNAME}-${PORTVERSION:R}${PORTVERSION:E}.src
 MAINTAINER=	ports@FreeBSD.org
 COMMENT=	A Verilog HDL simulator
 
+USES=		gmake
 USE_BZIP2=	yes
+
 BUILD_WRKSRC=	${WRKSRC}/src
-USE_GMAKE=	yes
 MAKEFILE=	makefile.freebsd
 
 PLIST_FILES=	bin/cver
 
-NO_STAGE=	yes
-.include <bsd.port.pre.mk>
-
 do-install:
-	${INSTALL_PROGRAM} ${WRKSRC}/bin/cver ${PREFIX}/bin
+	${INSTALL_PROGRAM} ${WRKSRC}/bin/cver ${STAGEDIR}${PREFIX}/bin
 
-.include <bsd.port.post.mk>
+.include <bsd.port.mk>
-- 
cgit