From 08bf1a57681fe65874df6f6da7d986d37d137cca Mon Sep 17 00:00:00 2001 From: bapt Date: Wed, 9 Apr 2014 09:49:02 +0000 Subject: Mark as broken unstaged perl ports With hat: portmgr --- cad/p5-Verilog-Perl/Makefile | 1 + 1 file changed, 1 insertion(+) (limited to 'cad/p5-Verilog-Perl') diff --git a/cad/p5-Verilog-Perl/Makefile b/cad/p5-Verilog-Perl/Makefile index 7f9ec722107b..5fdf4d71bf89 100644 --- a/cad/p5-Verilog-Perl/Makefile +++ b/cad/p5-Verilog-Perl/Makefile @@ -12,6 +12,7 @@ COMMENT= Building point for Verilog support in the Perl language BUILD_DEPENDS= flex>=2.5.35:${PORTSDIR}/textproc/flex +BROKEN= not staged USES= bison gmake perl5 USE_PERL5= configure -- cgit