From 5aba0e8d2037fdeb482b2c1de2c768df288a84f6 Mon Sep 17 00:00:00 2001
From: bapt <bapt@FreeBSD.org>
Date: Mon, 2 Mar 2015 23:09:43 +0000
Subject: Remove Authors from pkg-descr

---
 cad/verilog-mode.el/pkg-descr | 1 -
 1 file changed, 1 deletion(-)

(limited to 'cad/verilog-mode.el')

diff --git a/cad/verilog-mode.el/pkg-descr b/cad/verilog-mode.el/pkg-descr
index 3b1cd432f249..21bddb3f6125 100644
--- a/cad/verilog-mode.el/pkg-descr
+++ b/cad/verilog-mode.el/pkg-descr
@@ -6,5 +6,4 @@ Recent versions allow you to insert AUTOS in non-AUTO designs, so IP
 interconnect can be easily modified. You can also expand Verilog-2001 ".*"
 instantiations, to see what ports will be connected by simulators.
 
-Author:	Michael McNamara <mac@verilog.com>, Wilson Snyder <wsnyder@wsnyder.org>
 WWW: http://www.veripool.org/wiki/verilog-mode
-- 
cgit