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| author | amdmi3 <amdmi3@FreeBSD.org> | 2018-10-19 17:30:10 +0800 |
|---|---|---|
| committer | amdmi3 <amdmi3@FreeBSD.org> | 2018-10-19 17:30:10 +0800 |
| commit | 113294d58bb3d6096e8c43cbc770cf12aa850a66 (patch) | |
| tree | 0704ada39577866292eee886c10273a5cf0f7646 | |
| parent | 5ca4d552e37cd9eba579e30f37ab7baecd27144e (diff) | |
| download | freebsd-ports-gnome-113294d58bb3d6096e8c43cbc770cf12aa850a66.tar.gz freebsd-ports-gnome-113294d58bb3d6096e8c43cbc770cf12aa850a66.tar.zst freebsd-ports-gnome-113294d58bb3d6096e8c43cbc770cf12aa850a66.zip | |
- Update WWW
Approved by: portmgr blanket
| -rw-r--r-- | cad/verilog-mode.el/pkg-descr | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/cad/verilog-mode.el/pkg-descr b/cad/verilog-mode.el/pkg-descr index 21bddb3f6125..77062c89de70 100644 --- a/cad/verilog-mode.el/pkg-descr +++ b/cad/verilog-mode.el/pkg-descr @@ -6,4 +6,4 @@ Recent versions allow you to insert AUTOS in non-AUTO designs, so IP interconnect can be easily modified. You can also expand Verilog-2001 ".*" instantiations, to see what ports will be connected by simulators. -WWW: http://www.veripool.org/wiki/verilog-mode +WWW: https://www.veripool.org/wiki/verilog-mode |