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authorantoine <antoine@FreeBSD.org>2014-01-21 04:55:14 +0800
committerantoine <antoine@FreeBSD.org>2014-01-21 04:55:14 +0800
commit1907fc7cd4d4cbebfcdff46f8ecb197e94f1b359 (patch)
treed83f9ef91509d6e36023d15fa626cd70b7ee2abf
parent9425417c28478b28fd7f8e839e6f3ba115cffbe3 (diff)
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Stage support
-rw-r--r--cad/verilog-mode.el/Makefile6
1 files changed, 2 insertions, 4 deletions
diff --git a/cad/verilog-mode.el/Makefile b/cad/verilog-mode.el/Makefile
index 2101c0ef13be..48f26e0c3f00 100644
--- a/cad/verilog-mode.el/Makefile
+++ b/cad/verilog-mode.el/Makefile
@@ -26,10 +26,8 @@ EMACS_NO_BUILD_DEPENDS= yes
PLIST_FILES= ${EMACS_SITE_LISPDIR}/${PORTNAME}
-NO_STAGE= yes
do-install:
- @${MKDIR} ${PREFIX}/${EMACS_SITE_LISPDIR}
- ${INSTALL_DATA} ${WRKSRC}/${PORTNAME} ${PREFIX}/${EMACS_SITE_LISPDIR}
- @${CAT} ${PKGMESSAGE}
+ @${MKDIR} ${STAGEDIR}${PREFIX}/${EMACS_SITE_LISPDIR}
+ ${INSTALL_DATA} ${WRKSRC}/${PORTNAME} ${STAGEDIR}${PREFIX}/${EMACS_SITE_LISPDIR}
.include <bsd.port.mk>