[NEW PORT] cad/gplcver: A Verilog HDL simulator

	GPL Cver is a full 1995 P1364 Verilog standard HDL simulator.
	It also implements some of the 2001 P1364 standard features
	including all three PLI interfaces (tf_, acc_ and vpi_) as
	defined in the 2001 Language Reference Manual (LRM).

	Verilog is the name for both a language for describing
	electronic hardware called a hardware description language
	(HDL) and the name of the program that simulates HDL circuit
	descriptions to verify that described circuits will function
	correctly when the are constructed. Verilog is used only
	for describing digital logic circuits. Other HDLs such as
	Spice are used for describing analog circuits. There is an
	IEEE standard named P1364 that standardizes the Verilog HDL
	and the behavior of Verilog simulators.  Verilog is officially
	defined in the IEEE P1364 Language Reference Manual (LRM)
	that can be purchased from IEEE. There are many good books
	for learning that teach the Verilog HDL and/or that teach
	digital circuit design using Verilog.

	WWW: http://www.pragmatic-c.com/gpl-cver/

PR:		ports/80968
Submitted by:	Ying-Chieh Liao <ijliao@csie.nctu.edu.tw>

4 files changed, 50 insertions, 0 deletions

diff --git a/cad/Makefile b/cad/Makefile
index f6333aa3fca6..0ea7c9abed2c 100644
--- a/cad/Makefile
+++ b/cad/Makefile
@@ -26,6 +26,7 @@
     SUBDIR += gmsh
     SUBDIR += gnetlist
     SUBDIR += gnucap
+    SUBDIR += gplcver
     SUBDIR += gschem
     SUBDIR += gtkwave
     SUBDIR += gwave
diff --git a/cad/gplcver/Makefile b/cad/gplcver/Makefile
new file mode 100644
index 000000000000..7edcc81d5a08
--- /dev/null
+++ b/cad/gplcver/Makefile
@@ -0,0 +1,28 @@
+# ex:ts=8
+# Ports collection makefile for:	gpl-cver
+# Date created:			May 13, 2005
+# Whom:				ijliao
+#
+# $FreeBSD$
+#
+
+PORTNAME=	gplcver
+PORTVERSION=	2.11.a
+CATEGORIES=	cad
+MASTER_SITES=	http://www.pragmatic-c.com/gpl-cver/downloads/
+DISTNAME=	${PORTNAME}-${PORTVERSION:R}${PORTVERSION:E}.src
+
+MAINTAINER=	ports@FreeBSD.org
+COMMENT=	A Verilog HDL simulator
+
+USE_BZIP2=	yes
+BUILD_WRKSRC=	${WRKSRC}/src
+USE_GMAKE=	yes
+MAKEFILE=	makefile.freebsd
+
+PLIST_FILES=	bin/cver
+
+do-install:
+	${INSTALL_PROGRAM} ${WRKSRC}/bin/cver ${PREFIX}/bin
+
+.include <bsd.port.mk>
diff --git a/cad/gplcver/distinfo b/cad/gplcver/distinfo
new file mode 100644
index 000000000000..0efac4ad6395
--- /dev/null
+++ b/cad/gplcver/distinfo
@@ -0,0 +1,3 @@
+MD5 (gplcver-2.11a.src.tar.bz2) = 4967e78c299bdfdb0c9f2dcd4803e734
+SHA256 (gplcver-2.11a.src.tar.bz2) = b64eea22f354bee2de09532309c6a1e3f3658c427fe2d063ef3921c1042fa380
+SIZE (gplcver-2.11a.src.tar.bz2) = 1189439
diff --git a/cad/gplcver/pkg-descr b/cad/gplcver/pkg-descr
new file mode 100644
index 000000000000..dadc523cdac9
--- /dev/null
+++ b/cad/gplcver/pkg-descr
@@ -0,0 +1,18 @@
+GPL Cver is a full 1995 P1364 Verilog standard HDL simulator. It also
+implements some of the 2001 P1364 standard features including all three
+PLI interfaces (tf_, acc_ and vpi_) as defined in the 2001 Language
+Reference Manual (LRM).
+
+Verilog is the name for both a language for describing electronic hardware
+called a hardware description language (HDL) and the name of the program
+that simulates HDL circuit descriptions to verify that described circuits
+will function correctly when the are constructed. Verilog is used only for
+describing digital logic circuits. Other HDLs such as Spice are used for
+describing analog circuits. There is an IEEE standard named P1364 that
+standardizes the Verilog HDL and the behavior of Verilog simulators.
+Verilog is officially defined in the IEEE P1364 Language Reference
+Manual (LRM) that can be purchased from IEEE. There are many good books
+for learning that teach the Verilog HDL and/or that teach digital circuit
+design using Verilog.
+
+WWW: http://www.pragmatic-c.com/gpl-cver/