The Verilog-Perl library is a building point for Verilog support in the Perl

language. It includes:
* Verilog::Getopt which parses command line options similar to C++ and VCS.
* Verilog::Language which knows the language keywords and parses numbers.
* Verilog::Netlist which builds netlists out of Verilog files. This allows
  easy scripts to determine things such as the hierarchy of modules.
* Verilog::Parser invokes callbacks for language tokens.
* Verilog::Preproc preprocesses the language, and allows reading
  post-processed files right from Perl without temporary files.
* vpassert inserts PLIish warnings and assertions for any simulator.
* vppreproc preprocesses the complete Verilog 2001 and SystemVerilog language.
* vrename renames and cross-references Verilog symbols. Vrename creates Verilog
  cross references and makes it easy to rename signal and module names across
  multiple files. Vrename uses a simple and efficient three step process.
  First, you run vrename to create a list of signals in the design. You then
  edit this list, changing as many symbols as you wish. Vrename is then run a
  second time to apply the changes.

WWW:	http://www.veripool.org/wiki/verilog-perl

PR:		ports/134124
Submitted by:	Otacílio de Araújo Ramos Neto <otacilio.neto at ee.ufcg.edu.br>

1 files changed, 1 insertions, 0 deletions

diff --git a/cad/Makefile b/cad/Makefile
index 767c85da2c1e..c2aefb8acc5a 100644
--- a/cad/Makefile
+++ b/cad/Makefile
@@ -63,6 +63,7 @@
     SUBDIR += opencascade-tutorial
     SUBDIR += oregano
     SUBDIR += p5-GDS2
+    SUBDIR += p5-Verilog-Perl
     SUBDIR += pcb
     SUBDIR += pdnmesh
     SUBDIR += pythoncad