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author | mmoll <mmoll@FreeBSD.org> | 2015-11-28 01:52:56 +0800 |
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committer | mmoll <mmoll@FreeBSD.org> | 2015-11-28 01:52:56 +0800 |
commit | e63098f772949938fb9b5de81856ed62ae100c9d (patch) | |
tree | 18cb9cf82e679d566c82963299ef257262bc1641 /security | |
parent | 118f28523cc604fd0a050abf210dc695c1ae7b7e (diff) | |
download | freebsd-ports-gnome-e63098f772949938fb9b5de81856ed62ae100c9d.tar.gz freebsd-ports-gnome-e63098f772949938fb9b5de81856ed62ae100c9d.tar.zst freebsd-ports-gnome-e63098f772949938fb9b5de81856ed62ae100c9d.zip |
security/gnupg1: fix build on arm
PR: 197793
Submitted by: Mikael Urankar <mikael.urankar@gmail.com>
Approved by: kuriyama (maintainer, timeout)
Diffstat (limited to 'security')
-rw-r--r-- | security/gnupg1/files/patch-mpi_longlong.h | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/security/gnupg1/files/patch-mpi_longlong.h b/security/gnupg1/files/patch-mpi_longlong.h new file mode 100644 index 000000000000..4e08c5033ae0 --- /dev/null +++ b/security/gnupg1/files/patch-mpi_longlong.h @@ -0,0 +1,39 @@ +--- mpi/longlong.h.orig 2014-06-30 16:46:23 UTC ++++ mpi/longlong.h +@@ -184,8 +184,8 @@ extern UDItype __udiv_qrnnd (); + #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ + __asm__ ("adds %1, %4, %5\n" \ + "adc %0, %2, %3" \ +- : "=r" ((USItype)(sh)), \ +- "=&r" ((USItype)(sl)) \ ++ : "=r" ((sh)), \ ++ "=&r" ((sl)) \ + : "%r" ((USItype)(ah)), \ + "rI" ((USItype)(bh)), \ + "%r" ((USItype)(al)), \ +@@ -193,8 +193,8 @@ extern UDItype __udiv_qrnnd (); + #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ + __asm__ ("subs %1, %4, %5\n" \ + "sbc %0, %2, %3" \ +- : "=r" ((USItype)(sh)), \ +- "=&r" ((USItype)(sl)) \ ++ : "=r" ((sh)), \ ++ "=&r" ((sl)) \ + : "r" ((USItype)(ah)), \ + "rI" ((USItype)(bh)), \ + "r" ((USItype)(al)), \ +@@ -221,10 +221,10 @@ extern UDItype __udiv_qrnnd (); + : "r0", "r1", "r2") + #else + #define umul_ppmm(xh, xl, a, b) \ +- __asm__ ("%@ Inlined umul_ppmm\n" \ +- "umull %r1, %r0, %r2, %r3" \ +- : "=&r" ((USItype)(xh)), \ +- "=r" ((USItype)(xl)) \ ++ __asm__ ( \ ++ "umull %1, %0, %2, %3" \ ++ : "=&r" ((xh)), \ ++ "=r" ((xl)) \ + : "r" ((USItype)(a)), \ + "r" ((USItype)(b)) \ + : "r0", "r1") |