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-rw-r--r--cad/iverilog/Makefile2
1 files changed, 1 insertions, 1 deletions
diff --git a/cad/iverilog/Makefile b/cad/iverilog/Makefile
index e441e1a25f97..f1048e3358d0 100644
--- a/cad/iverilog/Makefile
+++ b/cad/iverilog/Makefile
@@ -12,7 +12,7 @@ CATEGORIES= cad
MASTER_SITES= ftp://icarus.com/pub/eda/verilog/v${PORTVERSION}/
DISTNAME= verilog-${PORTVERSION}
-MAINTAINER= keichii@FreeBSD.org
+MAINTAINER= watchman@ludd.luth.se
COMMENT= A Verilog simulation and synthesis tool
USE_BISON= yes