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* Remove cad/freecad as it has been BROKEN for over 4 months.erwin2009-06-141-1/+0
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* The Verilog-Perl library is a building point for Verilog support in the Perlgarga2009-05-261-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | language. It includes: * Verilog::Getopt which parses command line options similar to C++ and VCS. * Verilog::Language which knows the language keywords and parses numbers. * Verilog::Netlist which builds netlists out of Verilog files. This allows easy scripts to determine things such as the hierarchy of modules. * Verilog::Parser invokes callbacks for language tokens. * Verilog::Preproc preprocesses the language, and allows reading post-processed files right from Perl without temporary files. * vpassert inserts PLIish warnings and assertions for any simulator. * vppreproc preprocesses the complete Verilog 2001 and SystemVerilog language. * vrename renames and cross-references Verilog symbols. Vrename creates Verilog cross references and makes it easy to rename signal and module names across multiple files. Vrename uses a simple and efficient three step process. First, you run vrename to create a list of signals in the design. You then edit this list, changing as many symbols as you wish. Vrename is then run a second time to apply the changes. WWW: http://www.veripool.org/wiki/verilog-perl PR: ports/134124 Submitted by: Otacílio de Araújo Ramos Neto <otacilio.neto at ee.ufcg.edu.br>
* - Add port for verilog-mode.el, Emacs Verilog editing mode.stas2009-01-121-0/+1
| | | | WWW: http://www.veripool.org/wiki/verilog-mode
* Adding Gmsh with support of OpenCascade.thierry2008-12-311-0/+1
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* BasicDSP is an educational tool that makes it easy to experiment with simpledb2008-08-181-0/+1
| | | | | | | Digital Signal Processing algorithms for audio signals. The input can either be taken from the sound card, or be a locally generated sine wave, white noise or impulse signal. The output is fed to the sound card, as well as to a virtual oscilloscope and spectrum analyzer.
* Add GTKWave 3.1.9 port.bms2008-05-031-0/+1
| | | | | | The 3.x train of GTKWave has significantly more new featured and bugfixes, but would require introducing PORTEPOCH to replace cad/gtkwave. [Timeout on feedback from cad/gtkwave maintainer.]
* FreeCAD is an OpenSource CAD/CAE, based on OpenCasCade, QT and Python.thierry2007-05-271-0/+1
| | | | | | | | | | | | It features some key concepts like macro recording, workbenches, ability to run as a server and dynamically loadable application extensions and it is designed to be platform independent. Warning: FreeCAD is still in ALPHA state and not in shape for end user usage! <http://juergen-riegel.net/FreeCAD/Docu/> Suggested by: Pedro F. Giffuni <giffunip (at) yahoo.com>
* GDT (graphics data text) format translator written in C/C++ thathrs2007-04-291-0/+1
| | | | | converts a binary gdsii file to a text format that is compact and easy to parse.
* p5-GDS2, a Perl module for quickly creating programs to read and/orhrs2007-04-291-0/+1
| | | | write GDS2 files.
* KLayout is a Qt-based GDS2 viewer.hrs2007-04-291-0/+1
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* FindHier is a road-map generator for Magic/CIF/gdsII/PCSTR/GED/TeX.hrs2007-04-291-0/+1
| | | | | | | | ---When you have a large number of or big layout/schematic/TeX files which have possibly many top cells made by other people, how can you manage those layout/schematic/TeXs? FH is written for that. It can be useful up to your imagination or shell programming skill. FH analyses the hidden hierarchies of those cells and shows you the hierarchy information.
* GDSreader is a simple Calma (GDSii) parser/printer tool.hrs2007-04-291-0/+1
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* 2007-04-12 cad/geda-projectmanager: project deadmiwi2007-04-231-1/+0
| | | | 2007-04-19 audio/xmpeg3: does not work
* A Qt based application for tutorial to Open CASCADE Technology.thierry2007-04-011-0/+1
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* Open CASCADE Technology is a software development platform freely available inthierry2007-04-011-0/+1
| | | | | | | | | | | | open source. It includes components for 3D surface and solid modeling, visualization, data exchange and rapid application development. Open CASCADE Technology can be best applied in development of numerical simulation software including CAD/CAM/CAE, AEC and GIS, as well as PDM applications. BUGS: the module WOK does not work, but the other modules (the most interesting parts) are OK.
* The SystemC Verification (SCV) library is an extension library to SystemCmiwi2006-12-221-0/+1
| | | | | | | | | | | | which adds advanced verification capabilities to SystemC, including constrained randomization, complex constraint solvers, data-structure creation, Transaction Level Modeling (TLM), concurrency, and dynamic resource allocation management. WWW: http://www.systemc.org/ PR: ports/106822 Submitted by: Peter Johnson
* The goals of the FreeHDL project are to develop a VHDL simulator that hasalepulver2006-11-061-0/+1
| | | | | | | | | | a graphical waveform viewer and a source level debugger. It also aims at VHDL-93 compliancy. The project is at a very early development stage. WWW: http://www.freehdl.seul.org/ PR: ports/104634 Submitted by: lon_kamikaze at gmx.de
* Electric is a sophisticated electrical CAD system that can handlestas2006-09-301-0/+1
| | | | | | | | | | | | | | many forms of circuit design, including: - Custom IC layout (ASICs) - Schematic drawing - Hardware description language specifications Author: Static Free Software & Sun Microsystems, Inc. WWW: http://www.staticfreesoft.com/ PR: ports/100355 Submitted by: me (stas) Approved by: sem (mentor)
* This port provides a GUI for two freely available SPICE electronic circuititetcu2006-08-021-0/+1
| | | | | | | | | | | | | | | | | | | | | simulation engines: GNU-Cap and Ng-Spice. Current features: Import gschem schematic files using gentlist. Load and parse circuit description (net list) files. Provides a GUI interface for GNU-Cap OP, DC, AC and Transient analyses and generates appropriate simulator commands based on user input. Provides a GUI interface for Ng-Spice DC, AC and Transient analyses and generates appropriate simulator commands based on user input. The raw output may be viewed for any processes initiated by gspiceui. Formatting of simulator output so that it may be plotted using gwave. WWW: http://www.geda.seul.org/tools/gspiceui/index.html PR: ports/99357 Submitted by: Stanislav Sedov <ssedov at mbsd.msk.ru>
* ADMS is a code generator that converts electrical compact device modelsitetcu2006-07-301-0/+1
| | | | | | | | | | specified in high-level description language into ready-to-compile c code for the API of spice simulators. WWW: http://mot-adms.sourceforge.net/ PR: ports/101014 Submitted by: Stanislav Sedov <ssedov at mbsd.msk.ru>
* - gschem -> geda-gschemrafan2006-07-161-2/+2
| | | | | | | - gnetlist -> geda-netlist PR: ports/100222, ports/100230 Submitted by: maintainer
* Jspice3 is a circuit simulator developed to meet the needs of researchersitetcu2006-07-121-0/+1
| | | | | | | | | | | | | | | | | | | | | | | working with superconducting Josephson junction circuits, yet the program has the flexibility and power to meet the needs of other technologies. Jspice3 is an adaptation of the Berkeley Spice3f4 program, with added features. One added feature is a built-in graphical input front end for schematic capture. While displayed, simulations can be run and data plotted through this graphical interface. While not as powerful or as pretty as the Xic graphical interface, it holds its own in functionality. A significantly enhanced output plotting capability is provided, and Jspice3 has enhanced script interpretation capability. WWW: http://www.wrcad.com/jspice3.html PR: ports/93958 Submitted by: Pedro F. Giffuni Pedro can't maintain this port anymore and Stanislav Sedov agree to maintiant it.
* Various examples for gEDA suite. This includes:garga2006-07-041-0/+1
| | | | | | | | | | | | 1) gTAG - USB to JTAG interface 2) lightning_detector - a lightning detector 3) RF_Amp - schematics and associated materials for a SPICE model 4) TwoStageAmp - a two stage amplifier SPICE playpen WWW: http://www.geda.seul.org PR: ports/99564 Submitted by: Stanislav Sedov <ssedov@mbsd.msk.ru>
* Various documentation for gEDA suite, including architecture-relatedgarga2006-07-041-0/+1
| | | | | | | | | docs as well as examples of usage and tutorials. WWW: http://www.geda.seul.org PR: ports/99565 Submitted by: Stanislav Sedov <ssedov@mbsd.msk.ru>
* The gEDA project manager suite.pav2006-06-271-0/+1
| | | | | | | WWW: http://www.geda.seul.org PR: ports/99481 Submitted by: Stanislav Sedov <ssedov@mbsd.msk.ru>
* Gattrib is gEDA's attribute editor.pav2006-06-271-0/+1
| | | | | | | WWW: http://www.geda.seul.org PR: ports/99480 Submitted by: Stanislav Sedov <ssedov@mbsd.msk.ru>
* TclSpice is an improved version of Berkeley Spice designed to be used withpav2006-06-271-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | the Tcl/Tk scripting language. The project is open-source (BSD license) and based upon the NG-Spice source code base with many improvements Features and Improvements - Fully Tcl scriptable - installs with 'package require spice' statement - Hspice syntax (SpicePP). - GUI interfaces, various (Tk). - SpiceWish (BLT graph widget) - BLT (tcl compatible) vectors for storage, manipulation and arithmetic upon Spice waveforms. - Xspice additions (Georgia Tech). - Trigger upon waveform events. - Spice 'simulator state' save and restore for rapid 'what-if' simulations (no longer need to re-simulate from the beginning each time a device value is changed). Author: Stefan Jones <stefan.jones@multigig.com> WWW: http://tclspice.sourceforge.net/ PR: ports/99399 Submitted by: Stanislav Sedov <ssedov@mbsd.msk.ru>
* Add feappv 2.0, finite Element Analysis Program "personal version".thierry2006-04-041-0/+1
| | | | | | | | | | | | | This is a FEA program used in a classic FEM book. A complete (commercial) version is available here: <http://www.ce.berkeley.edu/~rlt/feap/> The "personal version" is very limited, but it keeps the same format as the complete (commercial) version and cad/netgen can produce files for it. PR: ports/95210 Submitted by: Pedro F. Giffuni <giffunip (at) asme.org>
* SCOTCH is a software package and libraries for graph, mesh and hypergraphthierry2006-02-041-0/+1
| | | | | | | | | | | | partitioning, static mapping, and sparse matrix block ordering. Its purpose of Scotch is to apply graph theory, with a divide and conquer approach, to scientific computing problems such as graph and mesh partitioning, static mapping, and sparse matrix ordering, in application domains ranging from structural mechanics to operating systems or bio-chemistry. Note: there is an older tarball included in Aster's distfile, but I prefer a separate distfile from the official site.
* [NEW PORT] cad/gplcver: A Verilog HDL simulatoredwin2005-12-291-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | GPL Cver is a full 1995 P1364 Verilog standard HDL simulator. It also implements some of the 2001 P1364 standard features including all three PLI interfaces (tf_, acc_ and vpi_) as defined in the 2001 Language Reference Manual (LRM). Verilog is the name for both a language for describing electronic hardware called a hardware description language (HDL) and the name of the program that simulates HDL circuit descriptions to verify that described circuits will function correctly when the are constructed. Verilog is used only for describing digital logic circuits. Other HDLs such as Spice are used for describing analog circuits. There is an IEEE standard named P1364 that standardizes the Verilog HDL and the behavior of Verilog simulators. Verilog is officially defined in the IEEE P1364 Language Reference Manual (LRM) that can be purchased from IEEE. There are many good books for learning that teach the Verilog HDL and/or that teach digital circuit design using Verilog. WWW: http://www.pragmatic-c.com/gpl-cver/ PR: ports/80968 Submitted by: Ying-Chieh Liao <ijliao@csie.nctu.edu.tw>
* Add systemc 2.1.v1, a modeling platform for system-level C++ models.lawrance2005-12-181-0/+1
| | | | | PR: ports/89987 Submitted by: Daniel Thiele
* Add Kicad, a software for the creation of electronic schematicthierry2005-12-091-0/+1
| | | | | | | | | | | | diagrams and printed circuit board artwork. Kicad is a set of four softwares and a project manager: * Eeschema: Schematic entry. * Pcbnew: Board editor. * Gerbview: GERBER viewer (photoplotter documents). * Cvpcb: footprint selector for components used in the circuit design. * Kicad: project manager.
* Remove expired portskris2005-11-051-1/+0
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* Move recently added port cad/fig2sxd to a new and more accurate categorygarga2005-09-081-1/+0
| | | | | | | graphics, with extra category converters. Pointed by: danfe Approved by: maintainer
* Add fig2sxd 0.13, convert .xfig files to the OpenOffice draw format.garga2005-09-081-0/+1
| | | | | PR: ports/85794 Submitted by: Emanuel Haupt <ehaupt@critical.ch>
* Graphical circuit design and simulation tool.des2005-06-121-0/+1
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* Add linux-gid 7.4.9b,barner2005-03-161-0/+1
| | | | | | | | | a graphical pre- and post-processor for numerical simulation programs. PR: ports/78383 Submitted by: Pedro Giffuni Approved by: arved (mentor)
* add impact 0.5.3ijliao2005-03-041-0/+1
| | | | Dynamic Finite Element Program Suite
* Add brlcad 7.0.4, CSG modelling system from the US Balisticthierry2005-02-211-0/+1
| | | | | | | Research Laboratory. PR: 76122 Submitted by: Pedro F. Giffuni
* Add z88 11.0, a compact Finite Element Analysis System.thierry2005-01-231-0/+1
| | | | | PR: 75698 Submitted by: Pedro F. Giffuni.
* Add triangle 1.5, a Two-Dimensional Quality Mesh Generator andthierry2004-11-161-1/+0
| | | | | | | | | Delaunay Triangulator. Change category from cad to math. Requested by: Pedro F. Giffuni Approved by: marcus
* Add triangle 1.5, a Two-Dimensional Quality Mesh Generator andthierry2004-11-151-0/+1
| | | | Delaunay Triangulator.
* add dxf2fig 2.07ijliao2004-08-261-0/+1
| | | | DXF to FIG converter
* Add dinotrace, a mature signal waveform viewer used to debug digital designpav2004-07-061-0/+1
| | | | | | | simulations. PR: ports/68688 Submitted by: Joachim Strombergson <watchman@ludd.ltu.se>
* Add cad/alliance, which is a complete set of free CAD tools andhrs2004-05-141-0/+1
| | | | | | | | portable libraries for VLSI design. It includes a VHDL compiler and simulator, logic synthesis tools, automatic place and route tools, and portable CMOS libraries. Approved by: linimon (mentor)
* Add netgen 4.3.1, an automatic 3D tetrahedral mesh generator.thierry2004-05-061-0/+1
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* Remove category pkg/COMMENT files in favour of a COMMENT variable in thekris2004-04-021-0/+2
| | | | | | | category makefile. Submitted by: Matthew Seaman <m.seaman@infracaninophile.co.uk> PR: 59651
* add qcad-partslib the parts-library for qcad.mr2004-03-281-0/+1
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* Reorder those filesmat2004-03-211-1/+1
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* add fandango 0.2.5ijliao2004-02-201-0/+1
| | | | A python scripted 3D CAD application
* . Remove metis-edf after a repo copy to the math category.glewis2003-12-101-1/+0
| | | | | PR: 58178 Submitted by: Pedro F. Giffuni <giffunip@yahoo.com>
* add pythoncad release 10ijliao2003-11-121-0/+1
| | | | An open-source CAD package built designed around Python
* . Remove kaskade port after repo copy to math category.glewis2003-11-081-1/+0
| | | | | PR: 58178 Submitted by: Pedro F. Giffuni <giffunip@yahoo.com>
* . Remove felt port now its been repo copied to the science category.glewis2003-11-081-1/+0
| | | | | PR: 58178 Submitted by: Pedro F. Giffuni <giffunip@yahoo.com>
* NEW port CAD/admeshedwin2003-10-101-0/+1
| | | | | | | A tool to analyze STL (stereolitholigraphy) files. PR: ports/52997 Submitted by: Pedro F. Giffuni <giffunip@yahoo.com>
* As announced on May 6, remove the broken sis port.kris2003-08-081-1/+0
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* As announced on May 6, remove the broken pisces port.kris2003-08-081-1/+0
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* Add gmsh 1.45.1, an automatic 3D finite element mesh generator.oliver2003-07-231-0/+1
| | | | | PR: 52201 Submitted by: Pedro Giffuni <giffunip@yahoo.com>
* Add astk-client , graphical interface for Code_Aster (client side).oliver2003-07-231-0/+1
| | | | | PR: 54765 Submitted by: thierry@pompo.net
* Add astk-serveur 1.0.14,oliver2003-07-231-0/+1
| | | | | | | | graphical interface for Code_Aster (server side). PR: 54764 Submitted by: thierry@pompo.net
* Add metis-edf 3, meshes partionning tool used by Code_Aster.oliver2003-07-231-0/+1
| | | | | PR: 53909 Submitted by: thierry@pompo.net
* Add new port cad/tochnogmaho2003-07-131-0/+1
| | | | | | | | | | tochnog is a free finite element program with many features which is distributed under GPL. TOCHNOG accepts free format input. Boundary conditions can be imposed at geometrical entities, as well as nodes and elements. PR: 52088 Submitted by: Pedro F. Giffuni <giffunip@yahoo.com>
* NEW port CAD/varkonedwin2003-05-211-0/+1
| | | | | | | | | A free CAD system and high level development tool for Engineering. It's a very interesting port for some branches of engineering. PR: ports/52202 Submitted by: Pedro F. Giffuni <giffunip@yahoo.com>
* A Three-Dimensional Structural Finite Element Programmaho2003-05-051-0/+1
| | | | | Submitted by : Pedro F. Giffuni <giffunip@yahoo.com> Almost writeen by: maho
* add ziarc 20020729ijliao2003-02-101-0/+1
| | | | ZiaRC is a Resistor Calculator
* add chipvault 200211ijliao2003-01-291-0/+1
| | | | A project organizer for VHDL and Verilog RTL hardware designs
* new port: cad/gwaveedwin2003-01-191-0/+1
| | | | | | | | Gwave is a waveform viewer. Its purpose is for viewing analog data, such as the output from Spice-like simulations. PR: ports/39364 Submitted by: Duncan Barclay <dmlb@dmlb.org>
* New port atlc version 4.0.1: A tool to calculate the impedance oflioux2002-11-141-0/+1
| | | | | | transmission lines Submitted by: blackend
* New port cascade version 1.4: A simple tool to analyze noise andlioux2002-11-141-0/+1
| | | | | | distortion of a RF system Submitted by: blackend
* add geda-utilsijliao2002-10-111-0/+1
| | | | | | | gEDA utilities PR: 43563 Submitted by: bruno <bruno@mail.tinkerbox.org>
* add geda-symcheckijliao2002-10-111-0/+1
| | | | | | | gEDA symbol checking utility PR: 43563 Submitted by: bruno <bruno@mail.tinkerbox.org>
* add transcalc 0.13ijliao2002-09-061-0/+1
| | | | A analysis and synthesis tool for RF and microwave transmission lines
* add gerbv 0.0.9ijliao2002-07-161-0/+1
| | | | A Free Gerber Viewer
* Remove acs. Its successor, gnucap, is already in the tree.tg2002-06-271-1/+0
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* add gtkwave 2.0.0p1ijliao2002-05-121-0/+1
| | | | Electronic Waveform Viewer
* add qfsm 0.30ijliao2002-04-121-0/+1
| | | | A graphical tool for designing finite state machines
* Add leocad 0.73, a CAD program that uses bricks similar to thosepetef2002-03-031-0/+1
| | | | | | | found in many toys. PR: 35231 Submitted by: David Yeske <dyeske@yahoo.com>
* Initial import of ngspice_reworkkevlo2002-02-091-0/+1
| | | | | | | Ngspice_rework is a circuit simulator derived from spice3f5. PR: 34589 Submitted by: AMAKAWA Shuhei <amakawa@jp.FreeBSD.org>
* add slffea 1.25ijliao2002-02-091-0/+1
| | | | San Le's Free Finite Element Analysis
* add gnucap 0.30ijliao2002-02-071-0/+1
| | | | The Gnu Circuit Analysis Package
* Add linux-eagle , an easy to use, yet powerful tool for designingsobomax2001-12-271-0/+1
| | | | printed circuit boards.
* add qmlsijliao2001-12-101-0/+1
| | | | Quine-McCluskey Logic Simplifier
* add pdnmeshijliao2001-10-151-0/+1
| | | | | | | A finite element program PR: 30115 Submitted by: Sarod Yatawatta <sarod@cs.pdn.ac.lk>
* gEDA electronic schematic capture toolsvanilla2001-04-071-0/+1
| | | | Submitted by: bruno.schwander@technologist.com
* gEDA electronic schematic capture toolsvanilla2001-04-071-0/+1
| | | | Submitted by: bruno.schwander@technologist.com
* geda-symbols is the basic component of geda package.vanilla2001-04-071-0/+1
| | | | Submitted byu.schwander@technologist.com
* libgeda is a a base library common to all the gEDA toolsvanilla2001-04-071-0/+1
| | | | Submitted by: bruno.schwander@technologist.com
* add vipecijliao2001-04-031-0/+1
| | | | ViPEC is a powerful tool for the analysis of high frequency, linear electrical networks
* Add oregano, schematic capture and simulation of electrical circuits.knu2001-03-071-0/+1
| | | | | PR: ports/25202 Submitted by: Anders Andersson <anders@codefactory.se>
* add iverilog, a Verilog simulation and synthesis toolijliao2001-02-131-0/+1
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* SCEPTRE (System for Circuit Evaluation and Prediction of Transientgrog2001-02-111-0/+1
| | | | | | | | | | Radiation Effects) is a general purpose circuit analysis program which provides all three major analyses, AC, DC, and transient analysis, on either linear or nonlinear networks. It employs a free-form input language and state variable methods to simulate problems of interest to electrical engineers. Requested-by: "Pedro F. Giffuni" <pfg1+@pitt.edu>
* Activate Electric.sada2000-07-301-0/+1
| | | | | PR: ports/18380 Submitted by: Mario Sergio Fujikawa Ferreira <lioux@linf.unb.br>
* Add PISCES, a two-dimensional device simulator which includesade2000-05-031-0/+1
| | | | | | | | | models for surface mobility, impact ionization and photo-generation. Quasi-three-dimensional simulation of cylindrically-symmetric devices is also supported. PR: 14686 Submitted by: Gianlorenzo Masini <masini@uniroma3.it>
* cider version 1b1steve1999-12-251-0/+1
| | | | | | | A mixed-level circuit and device simulator (includes SPICE3). PR: 15462 Submitted by: AMAKAWA Shuhei <amakawa@jp.FreeBSD.org>
* New port QCad, a 2D-CAD program. Uses Qt-2.tg1999-12-221-0/+1
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* Change Id->FreeBSD.obrien1999-08-251-1/+1
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* Activate the tkgate port.steve1999-06-071-1/+2
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* Sort entries. In particular, "large", "medium", "small" sort in this order,asami1998-12-071-2/+2
| | | | | | | | | | dispite their meanings. (Sometimes we're too smart for computers. :) Found by: sorting ports/INDEX by "sort -t '|' +1 -2" (Note: the whole "x11" category appears at the end with the above sort command, but I'll leave that the way it is for now -- "ls" shows it before other x11-* entries.)
* Activate geda.vanilla1998-12-061-1/+2
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* Enable sis, a new circuit emulator port.ghelmer1998-07-011-1/+2
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* Activate xcircuit.mph1998-05-181-1/+2
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* Activate kaskade.tg1997-11-171-1/+2
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* Add felt.asami1997-01-151-1/+2
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* Turn on mars and lprpsobrien1996-11-251-1/+2
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* Add spice.tg1996-05-231-1/+2
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* Add chipmunk, convert to new format along the way.asami1995-08-251-2/+6
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* Clean up subdir Makefiles. They now all look like this:asami1995-05-141-1/+2
| | | | | | | | | | | | | | | | | | | ===== # Id line # # RESTRICTED: restricted_port_1 (comment1) # RESTRICTED: restricted_port_2 (comment2) # # BROKEN: broken_port_3 (comment3) # BROKEN: broken_port_4 (comment4) # BROKEN: broken_port_5 (comment5) # SUBDIR= good_port_1 good_port_2 ... ===== Basically, the idea is to make it easy to find restricted or broken ports by doing a "grep".
* Alphabetize.jkh1995-01-131-2/+2
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* New cad groupjkh1995-01-131-0/+5
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