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* Fix build on sparcarved2006-01-201-4/+0
* BROKEN on sparc64: Does not compilekris2006-01-201-1/+7
* Fix maintainership (set to submitter)edwin2006-01-041-1/+1
* [NEW PORT] cad/gplcver: A Verilog HDL simulatoredwin2005-12-291-0/+28