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authorijliao <ijliao@FreeBSD.org>2001-02-13 19:02:15 +0800
committerijliao <ijliao@FreeBSD.org>2001-02-13 19:02:15 +0800
commit973b0f966966b1c5f668b423bd9a8b0d393a817d (patch)
tree70096d1271f3ba3bd32f52961dba5cff98d483f5 /astro/Makefile
parentf99b048d3747befa731d602bf674e0b22d4dce9c (diff)
downloadfreebsd-ports-graphics-973b0f966966b1c5f668b423bd9a8b0d393a817d.tar.gz
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add iverilog, a Verilog simulation and synthesis tool
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