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| author | bapt <bapt@FreeBSD.org> | 2015-03-03 07:09:43 +0800 |
|---|---|---|
| committer | bapt <bapt@FreeBSD.org> | 2015-03-03 07:09:43 +0800 |
| commit | 5aba0e8d2037fdeb482b2c1de2c768df288a84f6 (patch) | |
| tree | 4a53b0ddfff4111a274eeb0d7340133bc1afb7c4 /cad | |
| parent | 0fa4fa3e9e88567506cc091d2630ed608e561ba7 (diff) | |
| download | freebsd-ports-graphics-5aba0e8d2037fdeb482b2c1de2c768df288a84f6.tar.gz freebsd-ports-graphics-5aba0e8d2037fdeb482b2c1de2c768df288a84f6.tar.zst freebsd-ports-graphics-5aba0e8d2037fdeb482b2c1de2c768df288a84f6.zip | |
Remove Authors from pkg-descr
Diffstat (limited to 'cad')
| -rw-r--r-- | cad/verilog-mode.el/pkg-descr | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/cad/verilog-mode.el/pkg-descr b/cad/verilog-mode.el/pkg-descr index 3b1cd432f24..21bddb3f612 100644 --- a/cad/verilog-mode.el/pkg-descr +++ b/cad/verilog-mode.el/pkg-descr @@ -6,5 +6,4 @@ Recent versions allow you to insert AUTOS in non-AUTO designs, so IP interconnect can be easily modified. You can also expand Verilog-2001 ".*" instantiations, to see what ports will be connected by simulators. -Author: Michael McNamara <mac@verilog.com>, Wilson Snyder <wsnyder@wsnyder.org> WWW: http://www.veripool.org/wiki/verilog-mode |